aaa36a976b
This adds initial support for VI asics. This includes Iceland, Tonga, and Carrizo. Our inital focus as been Carrizo, so there are still gaps in support for Tonga and Iceland, notably power management. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
95 lines
3.2 KiB
C
95 lines
3.2 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __CZ_SMC_H__
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#define __CZ_SMC_H__
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#define MAX_NUM_FIRMWARE 8
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#define MAX_NUM_SCRATCH 11
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#define CZ_SCRATCH_SIZE_NONGFX_CLOCKGATING 1024
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#define CZ_SCRATCH_SIZE_NONGFX_GOLDENSETTING 2048
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#define CZ_SCRATCH_SIZE_SDMA_METADATA 1024
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#define CZ_SCRATCH_SIZE_IH ((2*256+1)*4)
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enum cz_scratch_entry {
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0 = 0,
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CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_PFP,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
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CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
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CZ_SCRATCH_ENTRY_UCODE_ID_GMCON_RENG,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_ARAM,
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CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
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CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_ERAM,
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CZ_SCRATCH_ENTRY_UCODE_ID_DMCU_IRAM,
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CZ_SCRATCH_ENTRY_UCODE_ID_POWER_PROFILING,
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CZ_SCRATCH_ENTRY_DATA_ID_SDMA_HALT,
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CZ_SCRATCH_ENTRY_DATA_ID_SYS_CLOCKGATING,
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CZ_SCRATCH_ENTRY_DATA_ID_SDMA_RING_REGS,
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CZ_SCRATCH_ENTRY_DATA_ID_NONGFX_REINIT,
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CZ_SCRATCH_ENTRY_DATA_ID_SDMA_START,
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CZ_SCRATCH_ENTRY_DATA_ID_IH_REGISTERS,
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CZ_SCRATCH_ENTRY_SMU8_FUSION_CLKTABLE
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};
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struct cz_buffer_entry {
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uint32_t data_size;
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uint32_t mc_addr_low;
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uint32_t mc_addr_high;
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void *kaddr;
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enum cz_scratch_entry firmware_ID;
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};
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struct cz_register_index_data_pair {
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uint32_t offset;
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uint32_t value;
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};
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struct cz_ih_meta_data {
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uint32_t command;
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struct cz_register_index_data_pair register_index_value_pair[1];
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};
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struct cz_smu_private_data {
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uint8_t driver_buffer_length;
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uint8_t scratch_buffer_length;
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uint16_t toc_entry_used_count;
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uint16_t toc_entry_initialize_index;
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uint16_t toc_entry_power_profiling_index;
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uint16_t toc_entry_aram;
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uint16_t toc_entry_ih_register_restore_task_index;
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uint16_t toc_entry_clock_table;
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uint16_t ih_register_restore_task_size;
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uint16_t smu_buffer_used_bytes;
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struct cz_buffer_entry toc_buffer;
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struct cz_buffer_entry smu_buffer;
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struct cz_buffer_entry driver_buffer[MAX_NUM_FIRMWARE];
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struct cz_buffer_entry scratch_buffer[MAX_NUM_SCRATCH];
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};
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#endif
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