Amanieu d'Antras 0b6a32ef88 riscv: Implement copy_thread_tls ... commit 20bda4ed62 upstream. This is required for clone3 which passes the TLS value through a struct rather than a register. Signed-off-by: Amanieu d'Antras <amanieu@gmail.com> Cc: linux-riscv@lists.infradead.org Cc: <stable@vger.kernel.org> # 5.3.x Link: https://lore.kernel.org/r/20200102172413.654385-6-amanieu@gmail.com Signed-off-by: Christian Brauner <christian.brauner@ubuntu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-01-14 20:08:34 +01:00
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boot	riscv: dts: HiFive Unleashed: add default chosen/stdout-path	2019-10-14 12:30:30 -07:00
configs	RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig	2019-09-19 05:44:35 -07:00
include	RISC-V: Add PCIe I/O BAR memory mapping	2019-10-28 10:43:32 -07:00
kernel	riscv: Implement copy_thread_tls	2020-01-14 20:08:34 +01:00
lib	riscv: Using CSR numbers to access CSRs	2019-08-30 11:04:19 -07:00
mm	riscv: add missing header file includes	2019-10-28 00:46:01 -07:00
net	bpf, riscv: Limit to 33 tail calls	2020-01-12 12:21:24 +01:00
Kbuild	riscv: add arch/riscv/Kbuild	2019-08-30 17:34:00 -07:00
Kconfig	riscv: Implement copy_thread_tls	2020-01-14 20:08:34 +01:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.socs	riscv: select SiFive platform drivers with SOC_SIFIVE	2019-07-01 13:20:01 -07:00
Makefile	Kbuild updates for v5.4	2019-09-20 08:36:47 -07:00