![Laurent Pinchart](/assets/img/avatar_default.png)
The passed mode must not be modified by the operation, make it const. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
1621 lines
42 KiB
C
1621 lines
42 KiB
C
/*
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* Copyright © 2006-2011 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*/
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#include <linux/i2c.h>
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#include <linux/pm_runtime.h>
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#include <drm/drmP.h>
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#include "framebuffer.h"
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#include "psb_drv.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_intel_display.h"
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#include "power.h"
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#include "cdv_device.h"
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struct cdv_intel_range_t {
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int min, max;
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};
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struct cdv_intel_p2_t {
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int dot_limit;
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int p2_slow, p2_fast;
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};
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struct cdv_intel_clock_t {
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/* given values */
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int n;
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int m1, m2;
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int p1, p2;
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/* derived values */
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int dot;
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int vco;
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int m;
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int p;
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};
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#define INTEL_P2_NUM 2
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struct cdv_intel_limit_t {
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struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
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struct cdv_intel_p2_t p2;
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};
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#define CDV_LIMIT_SINGLE_LVDS_96 0
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#define CDV_LIMIT_SINGLE_LVDS_100 1
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#define CDV_LIMIT_DAC_HDMI_27 2
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#define CDV_LIMIT_DAC_HDMI_96 3
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static const struct cdv_intel_limit_t cdv_intel_limits[] = {
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{ /* CDV_SIGNLE_LVDS_96MHz */
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.dot = {.min = 20000, .max = 115500},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 160},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 28, .max = 140},
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.p1 = {.min = 2, .max = 10},
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.p2 = {.dot_limit = 200000,
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.p2_slow = 14, .p2_fast = 14},
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},
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{ /* CDV_SINGLE_LVDS_100MHz */
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.dot = {.min = 20000, .max = 115500},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 160},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 28, .max = 140},
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.p1 = {.min = 2, .max = 10},
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/* The single-channel range is 25-112Mhz, and dual-channel
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* is 80-224Mhz. Prefer single channel as much as possible.
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*/
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.p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
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},
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{ /* CDV_DAC_HDMI_27MHz */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1809000, .max = 3564000},
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.n = {.min = 1, .max = 1},
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.m = {.min = 67, .max = 132},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 65, .max = 130},
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.p = {.min = 5, .max = 90},
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.p1 = {.min = 1, .max = 9},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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},
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{ /* CDV_DAC_HDMI_96MHz */
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.dot = {.min = 20000, .max = 400000},
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.vco = {.min = 1800000, .max = 3600000},
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.n = {.min = 2, .max = 6},
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.m = {.min = 60, .max = 160},
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.m1 = {.min = 0, .max = 0},
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.m2 = {.min = 58, .max = 158},
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.p = {.min = 5, .max = 100},
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.p1 = {.min = 1, .max = 10},
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.p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
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},
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};
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#define _wait_for(COND, MS, W) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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if (W && !in_dbg_master()) \
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msleep(W); \
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} \
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ret__; \
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})
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#define wait_for(COND, MS) _wait_for(COND, MS, 1)
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static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
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{
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int ret;
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle before read\n");
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return ret;
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}
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REG_WRITE(SB_ADDR, reg);
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REG_WRITE(SB_PCKT,
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SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
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SET_FIELD(SB_DEST_DPLL, SB_DEST) |
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SET_FIELD(0xf, SB_BYTE_ENABLE));
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle after read\n");
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return ret;
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}
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*val = REG_READ(SB_DATA);
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return 0;
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}
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static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
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{
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int ret;
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static bool dpio_debug = true;
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u32 temp;
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if (dpio_debug) {
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if (cdv_sb_read(dev, reg, &temp) == 0)
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DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
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DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
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}
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle before write\n");
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return ret;
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}
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REG_WRITE(SB_ADDR, reg);
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REG_WRITE(SB_DATA, val);
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REG_WRITE(SB_PCKT,
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SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
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SET_FIELD(SB_DEST_DPLL, SB_DEST) |
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SET_FIELD(0xf, SB_BYTE_ENABLE));
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ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
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if (ret) {
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DRM_ERROR("timeout waiting for SB to idle after write\n");
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return ret;
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}
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if (dpio_debug) {
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if (cdv_sb_read(dev, reg, &temp) == 0)
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DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
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}
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return 0;
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}
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/* Reset the DPIO configuration register. The BIOS does this at every
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* mode set.
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*/
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static void cdv_sb_reset(struct drm_device *dev)
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{
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REG_WRITE(DPIO_CFG, 0);
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REG_READ(DPIO_CFG);
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REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
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}
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/* Unlike most Intel display engines, on Cedarview the DPLL registers
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* are behind this sideband bus. They must be programmed while the
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* DPLL reference clock is on in the DPLL control register, but before
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* the DPLL is enabled in the DPLL control register.
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*/
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static int
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cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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struct cdv_intel_clock_t *clock, bool is_lvds)
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{
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struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_crtc->pipe;
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u32 m, n_vco, p;
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int ret = 0;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
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u32 ref_value;
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u32 lane_reg, lane_value;
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cdv_sb_reset(dev);
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REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
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udelay(100);
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/* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
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ref_value = 0x68A701;
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cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
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/* We don't know what the other fields of these regs are, so
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* leave them in place.
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*/
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/*
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* The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
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* for the pipe A/B. Display spec 1.06 has wrong definition.
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* Correct definition is like below:
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*
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* refclka mean use clock from same PLL
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*
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* if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
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*
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* if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
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*
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*/
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ret = cdv_sb_read(dev, ref_sfr, &ref_value);
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if (ret)
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return ret;
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ref_value &= ~(REF_CLK_MASK);
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/* use DPLL_A for pipeB on CRT/HDMI */
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if (pipe == 1 && !is_lvds) {
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DRM_DEBUG_KMS("use DPLLA for pipe B\n");
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ref_value |= REF_CLK_DPLLA;
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} else {
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DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
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ref_value |= REF_CLK_DPLL;
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}
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ret = cdv_sb_write(dev, ref_sfr, ref_value);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_M(pipe), &m);
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if (ret)
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return ret;
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m &= ~SB_M_DIVIDER_MASK;
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m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
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ret = cdv_sb_write(dev, SB_M(pipe), m);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
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if (ret)
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return ret;
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/* Follow the BIOS to program the N_DIVIDER REG */
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n_vco &= 0xFFFF;
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n_vco |= 0x107;
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n_vco &= ~(SB_N_VCO_SEL_MASK |
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SB_N_DIVIDER_MASK |
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SB_N_CB_TUNE_MASK);
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n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
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if (clock->vco < 2250000) {
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n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
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} else if (clock->vco < 2750000) {
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n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
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} else if (clock->vco < 3300000) {
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n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
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} else {
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n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
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n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
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}
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ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
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if (ret)
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return ret;
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ret = cdv_sb_read(dev, SB_P(pipe), &p);
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if (ret)
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return ret;
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p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
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p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
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switch (clock->p2) {
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case 5:
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p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
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break;
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case 10:
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p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
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break;
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case 14:
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p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
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break;
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case 7:
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p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
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break;
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default:
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DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
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return -EINVAL;
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}
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ret = cdv_sb_write(dev, SB_P(pipe), p);
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if (ret)
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return ret;
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lane_reg = PSB_LANE0;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE1;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE2;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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lane_reg = PSB_LANE3;
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cdv_sb_read(dev, lane_reg, &lane_value);
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lane_value &= ~(LANE_PLL_MASK);
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lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
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cdv_sb_write(dev, lane_reg, lane_value);
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return 0;
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}
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/*
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* Returns whether any encoder on the specified pipe is of the specified type
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*/
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static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *l_entry;
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list_for_each_entry(l_entry, &mode_config->connector_list, head) {
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if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
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struct psb_intel_encoder *psb_intel_encoder =
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psb_intel_attached_encoder(l_entry);
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if (psb_intel_encoder->type == type)
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return true;
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}
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}
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return false;
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}
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static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
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int refclk)
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{
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const struct cdv_intel_limit_t *limit;
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if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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/*
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* Now only single-channel LVDS is supported on CDV. If it is
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* incorrect, please add the dual-channel LVDS.
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*/
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if (refclk == 96000)
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limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
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else
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limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
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} else {
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if (refclk == 27000)
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limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
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else
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limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
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}
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return limit;
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}
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/* m1 is reserved as 0 in CDV, n is a ring counter */
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static void cdv_intel_clock(struct drm_device *dev,
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int refclk, struct cdv_intel_clock_t *clock)
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{
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clock->m = clock->m2 + 2;
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clock->p = clock->p1 * clock->p2;
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clock->vco = (refclk * clock->m) / clock->n;
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clock->dot = clock->vco / clock->p;
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}
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#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
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static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
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const struct cdv_intel_limit_t *limit,
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struct cdv_intel_clock_t *clock)
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{
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if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
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INTELPllInvalid("p1 out of range\n");
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if (clock->p < limit->p.min || limit->p.max < clock->p)
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INTELPllInvalid("p out of range\n");
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/* unnecessary to check the range of m(m1/M2)/n again */
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if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
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INTELPllInvalid("vco out of range\n");
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/* XXX: We may need to be checking "Dot clock"
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* depending on the multiplier, connector, etc.,
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* rather than just a single range.
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*/
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if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
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INTELPllInvalid("dot out of range\n");
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return true;
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}
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static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
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int refclk,
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struct cdv_intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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struct cdv_intel_clock_t clock;
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const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk);
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int err = target;
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if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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(REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
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/*
|
|
* For LVDS, if the panel is on, just rely on its current
|
|
* settings for dual-channel. We haven't figured out how to
|
|
* reliably set up different single/dual channel state, if we
|
|
* even can.
|
|
*/
|
|
if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
|
|
LVDS_CLKB_POWER_UP)
|
|
clock.p2 = limit->p2.p2_fast;
|
|
else
|
|
clock.p2 = limit->p2.p2_slow;
|
|
} else {
|
|
if (target < limit->p2.dot_limit)
|
|
clock.p2 = limit->p2.p2_slow;
|
|
else
|
|
clock.p2 = limit->p2.p2_fast;
|
|
}
|
|
|
|
memset(best_clock, 0, sizeof(*best_clock));
|
|
clock.m1 = 0;
|
|
/* m1 is reserved as 0 in CDV, n is a ring counter.
|
|
So skip the m1 loop */
|
|
for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
|
|
for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
|
|
clock.m2++) {
|
|
for (clock.p1 = limit->p1.min;
|
|
clock.p1 <= limit->p1.max;
|
|
clock.p1++) {
|
|
int this_err;
|
|
|
|
cdv_intel_clock(dev, refclk, &clock);
|
|
|
|
if (!cdv_intel_PLL_is_valid(crtc,
|
|
limit, &clock))
|
|
continue;
|
|
|
|
this_err = abs(clock.dot - target);
|
|
if (this_err < err) {
|
|
*best_clock = clock;
|
|
err = this_err;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return err != target;
|
|
}
|
|
|
|
static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
|
|
int x, int y, struct drm_framebuffer *old_fb)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
unsigned long start, offset;
|
|
u32 dspcntr;
|
|
int ret = 0;
|
|
|
|
if (!gma_power_begin(dev, true))
|
|
return 0;
|
|
|
|
/* no fb bound */
|
|
if (!crtc->fb) {
|
|
dev_err(dev->dev, "No FB bound\n");
|
|
goto psb_intel_pipe_cleaner;
|
|
}
|
|
|
|
|
|
/* We are displaying this buffer, make sure it is actually loaded
|
|
into the GTT */
|
|
ret = psb_gtt_pin(psbfb->gtt);
|
|
if (ret < 0)
|
|
goto psb_intel_pipe_set_base_exit;
|
|
start = psbfb->gtt->offset;
|
|
offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
|
|
|
|
REG_WRITE(map->stride, crtc->fb->pitches[0]);
|
|
|
|
dspcntr = REG_READ(map->cntr);
|
|
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
|
|
|
|
switch (crtc->fb->bits_per_pixel) {
|
|
case 8:
|
|
dspcntr |= DISPPLANE_8BPP;
|
|
break;
|
|
case 16:
|
|
if (crtc->fb->depth == 15)
|
|
dspcntr |= DISPPLANE_15_16BPP;
|
|
else
|
|
dspcntr |= DISPPLANE_16BPP;
|
|
break;
|
|
case 24:
|
|
case 32:
|
|
dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
|
|
break;
|
|
default:
|
|
dev_err(dev->dev, "Unknown color depth\n");
|
|
ret = -EINVAL;
|
|
goto psb_intel_pipe_set_base_exit;
|
|
}
|
|
REG_WRITE(map->cntr, dspcntr);
|
|
|
|
dev_dbg(dev->dev,
|
|
"Writing base %08lX %08lX %d %d\n", start, offset, x, y);
|
|
|
|
REG_WRITE(map->base, offset);
|
|
REG_READ(map->base);
|
|
REG_WRITE(map->surf, start);
|
|
REG_READ(map->surf);
|
|
|
|
psb_intel_pipe_cleaner:
|
|
/* If there was a previous display we can now unpin it */
|
|
if (old_fb)
|
|
psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
|
|
|
|
psb_intel_pipe_set_base_exit:
|
|
gma_power_end(dev);
|
|
return ret;
|
|
}
|
|
|
|
#define FIFO_PIPEA (1 << 0)
|
|
#define FIFO_PIPEB (1 << 1)
|
|
|
|
static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
|
|
{
|
|
struct drm_crtc *crtc;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = NULL;
|
|
|
|
crtc = dev_priv->pipe_to_crtc_mapping[pipe];
|
|
psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
|
|
if (crtc->fb == NULL || !psb_intel_crtc->active)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
static bool cdv_intel_single_pipe_active (struct drm_device *dev)
|
|
{
|
|
uint32_t pipe_enabled = 0;
|
|
|
|
if (cdv_intel_pipe_enabled(dev, 0))
|
|
pipe_enabled |= FIFO_PIPEA;
|
|
|
|
if (cdv_intel_pipe_enabled(dev, 1))
|
|
pipe_enabled |= FIFO_PIPEB;
|
|
|
|
|
|
DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
|
|
|
|
if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
|
|
return true;
|
|
else
|
|
return false;
|
|
}
|
|
|
|
static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
|
|
{
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
struct drm_connector *connector;
|
|
|
|
if (psb_intel_crtc->pipe != 1)
|
|
return false;
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
struct psb_intel_encoder *psb_intel_encoder =
|
|
psb_intel_attached_encoder(connector);
|
|
|
|
if (!connector->encoder
|
|
|| connector->encoder->crtc != crtc)
|
|
continue;
|
|
|
|
if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static void cdv_intel_disable_self_refresh (struct drm_device *dev)
|
|
{
|
|
if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
|
|
|
|
/* Disable self-refresh before adjust WM */
|
|
REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
|
|
REG_READ(FW_BLC_SELF);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
/* Cedarview workaround to write ovelay plane, which force to leave
|
|
* MAX_FIFO state.
|
|
*/
|
|
REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
|
|
REG_READ(OV_OVADD);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
}
|
|
|
|
}
|
|
|
|
static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc)
|
|
{
|
|
|
|
if (cdv_intel_single_pipe_active(dev)) {
|
|
u32 fw;
|
|
|
|
fw = REG_READ(DSPFW1);
|
|
fw &= ~DSP_FIFO_SR_WM_MASK;
|
|
fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
|
|
fw &= ~CURSOR_B_FIFO_WM_MASK;
|
|
fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
|
|
REG_WRITE(DSPFW1, fw);
|
|
|
|
fw = REG_READ(DSPFW2);
|
|
fw &= ~CURSOR_A_FIFO_WM_MASK;
|
|
fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
|
|
fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
|
|
fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
|
|
REG_WRITE(DSPFW2, fw);
|
|
|
|
REG_WRITE(DSPFW3, 0x36000000);
|
|
|
|
/* ignore FW4 */
|
|
|
|
if (is_pipeb_lvds(dev, crtc)) {
|
|
REG_WRITE(DSPFW5, 0x00040330);
|
|
} else {
|
|
fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
|
|
(4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
|
|
(3 << CURSOR_B_FIFO_WM1_SHIFT) |
|
|
(4 << CURSOR_FIFO_SR_WM1_SHIFT);
|
|
REG_WRITE(DSPFW5, fw);
|
|
}
|
|
|
|
REG_WRITE(DSPFW6, 0x10);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
/* enable self-refresh for single pipe active */
|
|
REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
|
|
REG_READ(FW_BLC_SELF);
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
} else {
|
|
|
|
/* HW team suggested values... */
|
|
REG_WRITE(DSPFW1, 0x3f880808);
|
|
REG_WRITE(DSPFW2, 0x0b020202);
|
|
REG_WRITE(DSPFW3, 0x24000000);
|
|
REG_WRITE(DSPFW4, 0x08030202);
|
|
REG_WRITE(DSPFW5, 0x01010101);
|
|
REG_WRITE(DSPFW6, 0x1d0);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
cdv_intel_disable_self_refresh(dev);
|
|
|
|
}
|
|
}
|
|
|
|
/** Loads the palette/gamma unit for the CRTC with the prepared values */
|
|
static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int palreg = PALETTE_A;
|
|
int i;
|
|
|
|
/* The clocks have to be on to load the palette. */
|
|
if (!crtc->enabled)
|
|
return;
|
|
|
|
switch (psb_intel_crtc->pipe) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
palreg = PALETTE_B;
|
|
break;
|
|
case 2:
|
|
palreg = PALETTE_C;
|
|
break;
|
|
default:
|
|
dev_err(dev->dev, "Illegal Pipe Number.\n");
|
|
return;
|
|
}
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
for (i = 0; i < 256; i++) {
|
|
REG_WRITE(palreg + 4 * i,
|
|
((psb_intel_crtc->lut_r[i] +
|
|
psb_intel_crtc->lut_adj[i]) << 16) |
|
|
((psb_intel_crtc->lut_g[i] +
|
|
psb_intel_crtc->lut_adj[i]) << 8) |
|
|
(psb_intel_crtc->lut_b[i] +
|
|
psb_intel_crtc->lut_adj[i]));
|
|
}
|
|
gma_power_end(dev);
|
|
} else {
|
|
for (i = 0; i < 256; i++) {
|
|
dev_priv->regs.pipe[0].palette[i] =
|
|
((psb_intel_crtc->lut_r[i] +
|
|
psb_intel_crtc->lut_adj[i]) << 16) |
|
|
((psb_intel_crtc->lut_g[i] +
|
|
psb_intel_crtc->lut_adj[i]) << 8) |
|
|
(psb_intel_crtc->lut_b[i] +
|
|
psb_intel_crtc->lut_adj[i]);
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Sets the power management mode of the pipe and plane.
|
|
*
|
|
* This code should probably grow support for turning the cursor off and back
|
|
* on appropriately at the same time as we're turning the pipe off/on.
|
|
*/
|
|
static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
u32 temp;
|
|
|
|
/* XXX: When our outputs are all unaware of DPMS modes other than off
|
|
* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
|
|
*/
|
|
cdv_intel_disable_self_refresh(dev);
|
|
|
|
switch (mode) {
|
|
case DRM_MODE_DPMS_ON:
|
|
case DRM_MODE_DPMS_STANDBY:
|
|
case DRM_MODE_DPMS_SUSPEND:
|
|
if (psb_intel_crtc->active)
|
|
return;
|
|
|
|
psb_intel_crtc->active = true;
|
|
|
|
/* Enable the DPLL */
|
|
temp = REG_READ(map->dpll);
|
|
if ((temp & DPLL_VCO_ENABLE) == 0) {
|
|
REG_WRITE(map->dpll, temp);
|
|
REG_READ(map->dpll);
|
|
/* Wait for the clocks to stabilize. */
|
|
udelay(150);
|
|
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
/* Wait for the clocks to stabilize. */
|
|
udelay(150);
|
|
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
/* Wait for the clocks to stabilize. */
|
|
udelay(150);
|
|
}
|
|
|
|
/* Jim Bish - switch plan and pipe per scott */
|
|
/* Enable the plane */
|
|
temp = REG_READ(map->cntr);
|
|
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
|
|
REG_WRITE(map->cntr,
|
|
temp | DISPLAY_PLANE_ENABLE);
|
|
/* Flush the plane changes */
|
|
REG_WRITE(map->base, REG_READ(map->base));
|
|
}
|
|
|
|
udelay(150);
|
|
|
|
/* Enable the pipe */
|
|
temp = REG_READ(map->conf);
|
|
if ((temp & PIPEACONF_ENABLE) == 0)
|
|
REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
|
|
|
|
temp = REG_READ(map->status);
|
|
temp &= ~(0xFFFF);
|
|
temp |= PIPE_FIFO_UNDERRUN;
|
|
REG_WRITE(map->status, temp);
|
|
REG_READ(map->status);
|
|
|
|
cdv_intel_update_watermark(dev, crtc);
|
|
cdv_intel_crtc_load_lut(crtc);
|
|
|
|
/* Give the overlay scaler a chance to enable
|
|
* if it's on this pipe */
|
|
/* psb_intel_crtc_dpms_video(crtc, true); TODO */
|
|
psb_intel_crtc->crtc_enable = true;
|
|
break;
|
|
case DRM_MODE_DPMS_OFF:
|
|
if (!psb_intel_crtc->active)
|
|
return;
|
|
|
|
psb_intel_crtc->active = false;
|
|
|
|
/* Give the overlay scaler a chance to disable
|
|
* if it's on this pipe */
|
|
/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
|
|
|
|
/* Disable the VGA plane that we never use */
|
|
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
|
|
|
/* Jim Bish - changed pipe/plane here as well. */
|
|
|
|
drm_vblank_off(dev, pipe);
|
|
/* Wait for vblank for the disable to take effect */
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
/* Next, disable display pipes */
|
|
temp = REG_READ(map->conf);
|
|
if ((temp & PIPEACONF_ENABLE) != 0) {
|
|
REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
|
|
REG_READ(map->conf);
|
|
}
|
|
|
|
/* Wait for vblank for the disable to take effect. */
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
udelay(150);
|
|
|
|
/* Disable display plane */
|
|
temp = REG_READ(map->cntr);
|
|
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
|
REG_WRITE(map->cntr,
|
|
temp & ~DISPLAY_PLANE_ENABLE);
|
|
/* Flush the plane changes */
|
|
REG_WRITE(map->base, REG_READ(map->base));
|
|
REG_READ(map->base);
|
|
}
|
|
|
|
temp = REG_READ(map->dpll);
|
|
if ((temp & DPLL_VCO_ENABLE) != 0) {
|
|
REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
}
|
|
|
|
/* Wait for the clocks to turn off. */
|
|
udelay(150);
|
|
cdv_intel_update_watermark(dev, crtc);
|
|
psb_intel_crtc->crtc_enable = false;
|
|
break;
|
|
}
|
|
/*Set FIFO Watermarks*/
|
|
REG_WRITE(DSPARB, 0x3F3E);
|
|
}
|
|
|
|
static void cdv_intel_crtc_prepare(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
|
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
}
|
|
|
|
static void cdv_intel_crtc_commit(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
|
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
|
|
}
|
|
|
|
static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
|
|
/**
|
|
* Return the pipe currently connected to the panel fitter,
|
|
* or -1 if the panel fitter is not present or not in use
|
|
*/
|
|
static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
|
|
{
|
|
u32 pfit_control;
|
|
|
|
pfit_control = REG_READ(PFIT_CONTROL);
|
|
|
|
/* See if the panel fitter is in use */
|
|
if ((pfit_control & PFIT_ENABLE) == 0)
|
|
return -1;
|
|
return (pfit_control >> 29) & 0x3;
|
|
}
|
|
|
|
static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode,
|
|
int x, int y,
|
|
struct drm_framebuffer *old_fb)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
int refclk;
|
|
struct cdv_intel_clock_t clock;
|
|
u32 dpll = 0, dspcntr, pipeconf;
|
|
bool ok;
|
|
bool is_crt = false, is_lvds = false, is_tv = false;
|
|
bool is_hdmi = false;
|
|
struct drm_mode_config *mode_config = &dev->mode_config;
|
|
struct drm_connector *connector;
|
|
|
|
list_for_each_entry(connector, &mode_config->connector_list, head) {
|
|
struct psb_intel_encoder *psb_intel_encoder =
|
|
psb_intel_attached_encoder(connector);
|
|
|
|
if (!connector->encoder
|
|
|| connector->encoder->crtc != crtc)
|
|
continue;
|
|
|
|
switch (psb_intel_encoder->type) {
|
|
case INTEL_OUTPUT_LVDS:
|
|
is_lvds = true;
|
|
break;
|
|
case INTEL_OUTPUT_TVOUT:
|
|
is_tv = true;
|
|
break;
|
|
case INTEL_OUTPUT_ANALOG:
|
|
is_crt = true;
|
|
break;
|
|
case INTEL_OUTPUT_HDMI:
|
|
is_hdmi = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (dev_priv->dplla_96mhz)
|
|
/* low-end sku, 96/100 mhz */
|
|
refclk = 96000;
|
|
else
|
|
/* high-end sku, 27/100 mhz */
|
|
refclk = 27000;
|
|
|
|
if (is_lvds && dev_priv->lvds_use_ssc) {
|
|
refclk = dev_priv->lvds_ssc_freq * 1000;
|
|
DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
|
|
}
|
|
|
|
drm_mode_debug_printmodeline(adjusted_mode);
|
|
|
|
ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
|
|
&clock);
|
|
if (!ok) {
|
|
dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
|
|
return 0;
|
|
}
|
|
|
|
dpll = DPLL_VGA_MODE_DIS;
|
|
if (is_tv) {
|
|
/* XXX: just matching BIOS for now */
|
|
/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
|
|
dpll |= 3;
|
|
}
|
|
/* dpll |= PLL_REF_INPUT_DREFCLK; */
|
|
|
|
dpll |= DPLL_SYNCLOCK_ENABLE;
|
|
/* if (is_lvds)
|
|
dpll |= DPLLB_MODE_LVDS;
|
|
else
|
|
dpll |= DPLLB_MODE_DAC_SERIAL; */
|
|
/* dpll |= (2 << 11); */
|
|
|
|
/* setup pipeconf */
|
|
pipeconf = REG_READ(map->conf);
|
|
|
|
/* Set up the display plane register */
|
|
dspcntr = DISPPLANE_GAMMA_ENABLE;
|
|
|
|
if (pipe == 0)
|
|
dspcntr |= DISPPLANE_SEL_PIPE_A;
|
|
else
|
|
dspcntr |= DISPPLANE_SEL_PIPE_B;
|
|
|
|
dspcntr |= DISPLAY_PLANE_ENABLE;
|
|
pipeconf |= PIPEACONF_ENABLE;
|
|
|
|
REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
|
|
REG_READ(map->dpll);
|
|
|
|
cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds);
|
|
|
|
udelay(150);
|
|
|
|
|
|
/* The LVDS pin pair needs to be on before the DPLLs are enabled.
|
|
* This is an exception to the general rule that mode_set doesn't turn
|
|
* things on.
|
|
*/
|
|
if (is_lvds) {
|
|
u32 lvds = REG_READ(LVDS);
|
|
|
|
lvds |=
|
|
LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
|
|
LVDS_PIPEB_SELECT;
|
|
/* Set the B0-B3 data pairs corresponding to
|
|
* whether we're going to
|
|
* set the DPLLs for dual-channel mode or not.
|
|
*/
|
|
if (clock.p2 == 7)
|
|
lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
|
|
else
|
|
lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
|
|
|
|
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
|
|
* appropriately here, but we need to look more
|
|
* thoroughly into how panels behave in the two modes.
|
|
*/
|
|
|
|
REG_WRITE(LVDS, lvds);
|
|
REG_READ(LVDS);
|
|
}
|
|
|
|
dpll |= DPLL_VCO_ENABLE;
|
|
|
|
/* Disable the panel fitter if it was on our pipe */
|
|
if (cdv_intel_panel_fitter_pipe(dev) == pipe)
|
|
REG_WRITE(PFIT_CONTROL, 0);
|
|
|
|
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
|
|
drm_mode_debug_printmodeline(mode);
|
|
|
|
REG_WRITE(map->dpll,
|
|
(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
/* Wait for the clocks to stabilize. */
|
|
udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
|
|
|
|
if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
|
|
dev_err(dev->dev, "Failed to get DPLL lock\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
{
|
|
int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
|
|
REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
|
|
}
|
|
|
|
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
|
|
((adjusted_mode->crtc_htotal - 1) << 16));
|
|
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
|
|
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
|
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
|
|
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
|
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
|
|
((adjusted_mode->crtc_vtotal - 1) << 16));
|
|
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
|
|
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
|
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
|
|
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
|
/* pipesrc and dspsize control the size that is scaled from,
|
|
* which should always be the user's requested size.
|
|
*/
|
|
REG_WRITE(map->size,
|
|
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
|
|
REG_WRITE(map->pos, 0);
|
|
REG_WRITE(map->src,
|
|
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
|
|
REG_WRITE(map->conf, pipeconf);
|
|
REG_READ(map->conf);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
REG_WRITE(map->cntr, dspcntr);
|
|
|
|
/* Flush the plane changes */
|
|
{
|
|
struct drm_crtc_helper_funcs *crtc_funcs =
|
|
crtc->helper_private;
|
|
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
|
}
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/**
|
|
* Save HW states of giving crtc
|
|
*/
|
|
static void cdv_intel_crtc_save(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
|
|
const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
|
|
uint32_t paletteReg;
|
|
int i;
|
|
|
|
if (!crtc_state) {
|
|
dev_dbg(dev->dev, "No CRTC state found\n");
|
|
return;
|
|
}
|
|
|
|
crtc_state->saveDSPCNTR = REG_READ(map->cntr);
|
|
crtc_state->savePIPECONF = REG_READ(map->conf);
|
|
crtc_state->savePIPESRC = REG_READ(map->src);
|
|
crtc_state->saveFP0 = REG_READ(map->fp0);
|
|
crtc_state->saveFP1 = REG_READ(map->fp1);
|
|
crtc_state->saveDPLL = REG_READ(map->dpll);
|
|
crtc_state->saveHTOTAL = REG_READ(map->htotal);
|
|
crtc_state->saveHBLANK = REG_READ(map->hblank);
|
|
crtc_state->saveHSYNC = REG_READ(map->hsync);
|
|
crtc_state->saveVTOTAL = REG_READ(map->vtotal);
|
|
crtc_state->saveVBLANK = REG_READ(map->vblank);
|
|
crtc_state->saveVSYNC = REG_READ(map->vsync);
|
|
crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
|
|
|
|
/*NOTE: DSPSIZE DSPPOS only for psb*/
|
|
crtc_state->saveDSPSIZE = REG_READ(map->size);
|
|
crtc_state->saveDSPPOS = REG_READ(map->pos);
|
|
|
|
crtc_state->saveDSPBASE = REG_READ(map->base);
|
|
|
|
DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
|
|
crtc_state->saveDSPCNTR,
|
|
crtc_state->savePIPECONF,
|
|
crtc_state->savePIPESRC,
|
|
crtc_state->saveFP0,
|
|
crtc_state->saveFP1,
|
|
crtc_state->saveDPLL,
|
|
crtc_state->saveHTOTAL,
|
|
crtc_state->saveHBLANK,
|
|
crtc_state->saveHSYNC,
|
|
crtc_state->saveVTOTAL,
|
|
crtc_state->saveVBLANK,
|
|
crtc_state->saveVSYNC,
|
|
crtc_state->saveDSPSTRIDE,
|
|
crtc_state->saveDSPSIZE,
|
|
crtc_state->saveDSPPOS,
|
|
crtc_state->saveDSPBASE
|
|
);
|
|
|
|
paletteReg = map->palette;
|
|
for (i = 0; i < 256; ++i)
|
|
crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
|
|
}
|
|
|
|
/**
|
|
* Restore HW states of giving crtc
|
|
*/
|
|
static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
|
|
const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
|
|
uint32_t paletteReg;
|
|
int i;
|
|
|
|
if (!crtc_state) {
|
|
dev_dbg(dev->dev, "No crtc state\n");
|
|
return;
|
|
}
|
|
|
|
DRM_DEBUG(
|
|
"current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
|
|
REG_READ(map->cntr),
|
|
REG_READ(map->conf),
|
|
REG_READ(map->src),
|
|
REG_READ(map->fp0),
|
|
REG_READ(map->fp1),
|
|
REG_READ(map->dpll),
|
|
REG_READ(map->htotal),
|
|
REG_READ(map->hblank),
|
|
REG_READ(map->hsync),
|
|
REG_READ(map->vtotal),
|
|
REG_READ(map->vblank),
|
|
REG_READ(map->vsync),
|
|
REG_READ(map->stride),
|
|
REG_READ(map->size),
|
|
REG_READ(map->pos),
|
|
REG_READ(map->base)
|
|
);
|
|
|
|
DRM_DEBUG(
|
|
"saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
|
|
crtc_state->saveDSPCNTR,
|
|
crtc_state->savePIPECONF,
|
|
crtc_state->savePIPESRC,
|
|
crtc_state->saveFP0,
|
|
crtc_state->saveFP1,
|
|
crtc_state->saveDPLL,
|
|
crtc_state->saveHTOTAL,
|
|
crtc_state->saveHBLANK,
|
|
crtc_state->saveHSYNC,
|
|
crtc_state->saveVTOTAL,
|
|
crtc_state->saveVBLANK,
|
|
crtc_state->saveVSYNC,
|
|
crtc_state->saveDSPSTRIDE,
|
|
crtc_state->saveDSPSIZE,
|
|
crtc_state->saveDSPPOS,
|
|
crtc_state->saveDSPBASE
|
|
);
|
|
|
|
|
|
if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
|
|
REG_WRITE(map->dpll,
|
|
crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
DRM_DEBUG("write dpll: %x\n",
|
|
REG_READ(map->dpll));
|
|
udelay(150);
|
|
}
|
|
|
|
REG_WRITE(map->fp0, crtc_state->saveFP0);
|
|
REG_READ(map->fp0);
|
|
|
|
REG_WRITE(map->fp1, crtc_state->saveFP1);
|
|
REG_READ(map->fp1);
|
|
|
|
REG_WRITE(map->dpll, crtc_state->saveDPLL);
|
|
REG_READ(map->dpll);
|
|
udelay(150);
|
|
|
|
REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
|
|
REG_WRITE(map->hblank, crtc_state->saveHBLANK);
|
|
REG_WRITE(map->hsync, crtc_state->saveHSYNC);
|
|
REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
|
|
REG_WRITE(map->vblank, crtc_state->saveVBLANK);
|
|
REG_WRITE(map->vsync, crtc_state->saveVSYNC);
|
|
REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
|
|
|
|
REG_WRITE(map->size, crtc_state->saveDSPSIZE);
|
|
REG_WRITE(map->pos, crtc_state->saveDSPPOS);
|
|
|
|
REG_WRITE(map->src, crtc_state->savePIPESRC);
|
|
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
|
REG_WRITE(map->conf, crtc_state->savePIPECONF);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
|
|
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
|
|
|
cdv_intel_wait_for_vblank(dev);
|
|
|
|
paletteReg = map->palette;
|
|
for (i = 0; i < 256; ++i)
|
|
REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
|
|
}
|
|
|
|
static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
|
|
struct drm_file *file_priv,
|
|
uint32_t handle,
|
|
uint32_t width, uint32_t height)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
|
|
uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
|
|
uint32_t temp;
|
|
size_t addr = 0;
|
|
struct gtt_range *gt;
|
|
struct drm_gem_object *obj;
|
|
int ret;
|
|
|
|
/* if we want to turn of the cursor ignore width and height */
|
|
if (!handle) {
|
|
/* turn off the cursor */
|
|
temp = CURSOR_MODE_DISABLE;
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
REG_WRITE(control, temp);
|
|
REG_WRITE(base, 0);
|
|
gma_power_end(dev);
|
|
}
|
|
|
|
/* unpin the old GEM object */
|
|
if (psb_intel_crtc->cursor_obj) {
|
|
gt = container_of(psb_intel_crtc->cursor_obj,
|
|
struct gtt_range, gem);
|
|
psb_gtt_unpin(gt);
|
|
drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
|
|
psb_intel_crtc->cursor_obj = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Currently we only support 64x64 cursors */
|
|
if (width != 64 || height != 64) {
|
|
dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
obj = drm_gem_object_lookup(dev, file_priv, handle);
|
|
if (!obj)
|
|
return -ENOENT;
|
|
|
|
if (obj->size < width * height * 4) {
|
|
dev_dbg(dev->dev, "buffer is to small\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
gt = container_of(obj, struct gtt_range, gem);
|
|
|
|
/* Pin the memory into the GTT */
|
|
ret = psb_gtt_pin(gt);
|
|
if (ret) {
|
|
dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
|
|
return ret;
|
|
}
|
|
|
|
addr = gt->offset; /* Or resource.start ??? */
|
|
|
|
psb_intel_crtc->cursor_addr = addr;
|
|
|
|
temp = 0;
|
|
/* set the pipe for the cursor */
|
|
temp |= (pipe << 28);
|
|
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
REG_WRITE(control, temp);
|
|
REG_WRITE(base, addr);
|
|
gma_power_end(dev);
|
|
}
|
|
|
|
/* unpin the old GEM object */
|
|
if (psb_intel_crtc->cursor_obj) {
|
|
gt = container_of(psb_intel_crtc->cursor_obj,
|
|
struct gtt_range, gem);
|
|
psb_gtt_unpin(gt);
|
|
drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
|
|
psb_intel_crtc->cursor_obj = obj;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
uint32_t temp = 0;
|
|
uint32_t adder;
|
|
|
|
|
|
if (x < 0) {
|
|
temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
|
|
x = -x;
|
|
}
|
|
if (y < 0) {
|
|
temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
|
|
y = -y;
|
|
}
|
|
|
|
temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
|
|
temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
|
|
|
|
adder = psb_intel_crtc->cursor_addr;
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
|
|
REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
|
|
gma_power_end(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
|
|
u16 *green, u16 *blue, uint32_t start, uint32_t size)
|
|
{
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int i;
|
|
int end = (start + size > 256) ? 256 : start + size;
|
|
|
|
for (i = start; i < end; i++) {
|
|
psb_intel_crtc->lut_r[i] = red[i] >> 8;
|
|
psb_intel_crtc->lut_g[i] = green[i] >> 8;
|
|
psb_intel_crtc->lut_b[i] = blue[i] >> 8;
|
|
}
|
|
|
|
cdv_intel_crtc_load_lut(crtc);
|
|
}
|
|
|
|
static int cdv_crtc_set_config(struct drm_mode_set *set)
|
|
{
|
|
int ret = 0;
|
|
struct drm_device *dev = set->crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
|
|
if (!dev_priv->rpm_enabled)
|
|
return drm_crtc_helper_set_config(set);
|
|
|
|
pm_runtime_forbid(&dev->pdev->dev);
|
|
|
|
ret = drm_crtc_helper_set_config(set);
|
|
|
|
pm_runtime_allow(&dev->pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
|
|
|
|
/* FIXME: why are we using this, should it be cdv_ in this tree ? */
|
|
|
|
static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
|
|
{
|
|
clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
|
|
clock->p = clock->p1 * clock->p2;
|
|
clock->vco = refclk * clock->m / (clock->n + 2);
|
|
clock->dot = clock->vco / clock->p;
|
|
}
|
|
|
|
/* Returns the clock of the currently programmed mode of the given pipe. */
|
|
static int cdv_intel_crtc_clock_get(struct drm_device *dev,
|
|
struct drm_crtc *crtc)
|
|
{
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
u32 dpll;
|
|
u32 fp;
|
|
struct cdv_intel_clock_t clock;
|
|
bool is_lvds;
|
|
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
dpll = REG_READ(map->dpll);
|
|
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
|
|
fp = REG_READ(map->fp0);
|
|
else
|
|
fp = REG_READ(map->fp1);
|
|
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
|
|
gma_power_end(dev);
|
|
} else {
|
|
dpll = p->dpll;
|
|
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
|
|
fp = p->fp0;
|
|
else
|
|
fp = p->fp1;
|
|
|
|
is_lvds = (pipe == 1) &&
|
|
(dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
|
|
}
|
|
|
|
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
|
|
clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
|
|
clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
|
|
|
|
if (is_lvds) {
|
|
clock.p1 =
|
|
ffs((dpll &
|
|
DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
|
|
DPLL_FPA01_P1_POST_DIV_SHIFT);
|
|
if (clock.p1 == 0) {
|
|
clock.p1 = 4;
|
|
dev_err(dev->dev, "PLL %d\n", dpll);
|
|
}
|
|
clock.p2 = 14;
|
|
|
|
if ((dpll & PLL_REF_INPUT_MASK) ==
|
|
PLLB_REF_INPUT_SPREADSPECTRUMIN) {
|
|
/* XXX: might not be 66MHz */
|
|
i8xx_clock(66000, &clock);
|
|
} else
|
|
i8xx_clock(48000, &clock);
|
|
} else {
|
|
if (dpll & PLL_P1_DIVIDE_BY_TWO)
|
|
clock.p1 = 2;
|
|
else {
|
|
clock.p1 =
|
|
((dpll &
|
|
DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
|
|
DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
|
|
}
|
|
if (dpll & PLL_P2_DIVIDE_BY_4)
|
|
clock.p2 = 4;
|
|
else
|
|
clock.p2 = 2;
|
|
|
|
i8xx_clock(48000, &clock);
|
|
}
|
|
|
|
/* XXX: It would be nice to validate the clocks, but we can't reuse
|
|
* i830PllIsValid() because it relies on the xf86_config connector
|
|
* configuration being accurate, which it isn't necessarily.
|
|
*/
|
|
|
|
return clock.dot;
|
|
}
|
|
|
|
/** Returns the currently programmed mode of the given pipe. */
|
|
struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
|
|
struct drm_crtc *crtc)
|
|
{
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
int pipe = psb_intel_crtc->pipe;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
|
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
|
struct drm_display_mode *mode;
|
|
int htot;
|
|
int hsync;
|
|
int vtot;
|
|
int vsync;
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
htot = REG_READ(map->htotal);
|
|
hsync = REG_READ(map->hsync);
|
|
vtot = REG_READ(map->vtotal);
|
|
vsync = REG_READ(map->vsync);
|
|
gma_power_end(dev);
|
|
} else {
|
|
htot = p->htotal;
|
|
hsync = p->hsync;
|
|
vtot = p->vtotal;
|
|
vsync = p->vsync;
|
|
}
|
|
|
|
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
|
|
if (!mode)
|
|
return NULL;
|
|
|
|
mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
|
|
mode->hdisplay = (htot & 0xffff) + 1;
|
|
mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
|
|
mode->hsync_start = (hsync & 0xffff) + 1;
|
|
mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
|
|
mode->vdisplay = (vtot & 0xffff) + 1;
|
|
mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
|
|
mode->vsync_start = (vsync & 0xffff) + 1;
|
|
mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
|
|
|
|
drm_mode_set_name(mode);
|
|
drm_mode_set_crtcinfo(mode, 0);
|
|
|
|
return mode;
|
|
}
|
|
|
|
static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
|
|
{
|
|
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
|
|
|
kfree(psb_intel_crtc->crtc_state);
|
|
drm_crtc_cleanup(crtc);
|
|
kfree(psb_intel_crtc);
|
|
}
|
|
|
|
const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
|
|
.dpms = cdv_intel_crtc_dpms,
|
|
.mode_fixup = cdv_intel_crtc_mode_fixup,
|
|
.mode_set = cdv_intel_crtc_mode_set,
|
|
.mode_set_base = cdv_intel_pipe_set_base,
|
|
.prepare = cdv_intel_crtc_prepare,
|
|
.commit = cdv_intel_crtc_commit,
|
|
};
|
|
|
|
const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
|
|
.save = cdv_intel_crtc_save,
|
|
.restore = cdv_intel_crtc_restore,
|
|
.cursor_set = cdv_intel_crtc_cursor_set,
|
|
.cursor_move = cdv_intel_crtc_cursor_move,
|
|
.gamma_set = cdv_intel_crtc_gamma_set,
|
|
.set_config = cdv_crtc_set_config,
|
|
.destroy = cdv_intel_crtc_destroy,
|
|
};
|