![Michel Dänzer](/assets/img/avatar_default.png)
This could previously fail if either of the enabled displays was using a horizontal resolution that is a multiple of 128, and only the leftmost column of the cursor was (supposed to be) visible at the right edge of that display. The solution is to move the cursor one pixel to the left in that case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33183 Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
307 lines
9.2 KiB
C
307 lines
9.2 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon.h"
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
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{
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struct radeon_device *rdev = crtc->dev->dev_private;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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uint32_t cur_lock;
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if (ASIC_IS_DCE4(rdev)) {
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cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
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else
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cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
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WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
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} else if (ASIC_IS_AVIVO(rdev)) {
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cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
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else
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cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
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WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
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} else {
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cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= RADEON_CUR_LOCK;
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else
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cur_lock &= ~RADEON_CUR_LOCK;
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
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}
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}
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static void radeon_hide_cursor(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
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} else {
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switch (radeon_crtc->crtc_id) {
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case 0:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
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break;
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case 1:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
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break;
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default:
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return;
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}
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WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
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}
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}
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static void radeon_show_cursor(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
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EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
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(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
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} else {
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switch (radeon_crtc->crtc_id) {
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case 0:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
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break;
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case 1:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
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break;
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default:
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return;
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}
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WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
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(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
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~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
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}
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}
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static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
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uint64_t gpu_addr)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
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upper_32_bits(gpu_addr));
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WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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gpu_addr & 0xffffffff);
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} else if (ASIC_IS_AVIVO(rdev)) {
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if (rdev->family >= CHIP_RV770) {
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if (radeon_crtc->crtc_id)
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WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
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else
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WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
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}
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WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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gpu_addr & 0xffffffff);
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} else {
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radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
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}
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}
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int radeon_crtc_cursor_set(struct drm_crtc *crtc,
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struct drm_file *file_priv,
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uint32_t handle,
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uint32_t width,
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uint32_t height)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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struct drm_gem_object *obj;
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struct radeon_bo *robj;
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uint64_t gpu_addr;
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int ret;
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if (!handle) {
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/* turn off cursor */
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radeon_hide_cursor(crtc);
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obj = NULL;
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goto unpin;
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}
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if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
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DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
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return -EINVAL;
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}
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obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
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if (!obj) {
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DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
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return -ENOENT;
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}
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robj = gem_to_radeon_bo(obj);
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ret = radeon_bo_reserve(robj, false);
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if (unlikely(ret != 0))
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goto fail;
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/* Only 27 bit offset for legacy cursor */
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ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
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ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
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&gpu_addr);
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radeon_bo_unreserve(robj);
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if (ret)
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goto fail;
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radeon_crtc->cursor_width = width;
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radeon_crtc->cursor_height = height;
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radeon_lock_cursor(crtc, true);
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radeon_set_cursor(crtc, obj, gpu_addr);
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radeon_show_cursor(crtc);
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radeon_lock_cursor(crtc, false);
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unpin:
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if (radeon_crtc->cursor_bo) {
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robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
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ret = radeon_bo_reserve(robj, false);
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if (likely(ret == 0)) {
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radeon_bo_unpin(robj);
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radeon_bo_unreserve(robj);
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}
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drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
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}
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radeon_crtc->cursor_bo = obj;
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return 0;
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fail:
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drm_gem_object_unreference_unlocked(obj);
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return ret;
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}
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int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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int x, int y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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int xorigin = 0, yorigin = 0;
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int w = radeon_crtc->cursor_width;
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if (ASIC_IS_AVIVO(rdev)) {
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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}
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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if (x < 0) {
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xorigin = min(-x, CURSOR_WIDTH - 1);
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x = 0;
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}
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if (y < 0) {
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yorigin = min(-y, CURSOR_HEIGHT - 1);
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y = 0;
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}
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if (ASIC_IS_AVIVO(rdev)) {
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int i = 0;
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struct drm_crtc *crtc_p;
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/* avivo cursor image can't end on 128 pixel boundary or
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* go past the end of the frame if both crtcs are enabled
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*/
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list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
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if (crtc_p->enabled)
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i++;
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}
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if (i > 1) {
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int cursor_end, frame_end;
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cursor_end = x - xorigin + w;
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frame_end = crtc->x + crtc->mode.crtc_hdisplay;
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if (cursor_end >= frame_end) {
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w = w - (cursor_end - frame_end);
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if (!(frame_end & 0x7f))
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w--;
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} else {
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if (!(cursor_end & 0x7f))
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w--;
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}
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if (w <= 0) {
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w = 1;
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cursor_end = x - xorigin + w;
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if (!(cursor_end & 0x7f)) {
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x--;
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WARN_ON_ONCE(x < 0);
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}
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}
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}
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}
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radeon_lock_cursor(crtc, true);
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else {
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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y *= 2;
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WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (xorigin << 16)
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| yorigin));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (x << 16)
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| y));
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
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(yorigin * 256)));
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}
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radeon_lock_cursor(crtc, false);
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return 0;
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}
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