63fba242c4
The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter. The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq. The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a log period of time, producing display glitches. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191021091509.3864-5-narmstrong@baylibre.com
22 lines
596 B
C
22 lines
596 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef __MESON_RDMA_H
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#define __MESON_RDMA_H
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#include "meson_drv.h"
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int meson_rdma_init(struct meson_drm *priv);
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void meson_rdma_free(struct meson_drm *priv);
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void meson_rdma_setup(struct meson_drm *priv);
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void meson_rdma_reset(struct meson_drm *priv);
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void meson_rdma_stop(struct meson_drm *priv);
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void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg);
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void meson_rdma_flush(struct meson_drm *priv);
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#endif /* __MESON_RDMA_H */
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