![Prarit Bhargava](/assets/img/avatar_default.png)
commit aa297292d7
("x86/tsc: Enumerate SKL cpu_khz and tsc_khz via
CPUID") added code to retrieve the crystal and TSC frequency from CPUID
leaves. If the crystal freqency is enumerated as 0,the resulting TSC
frequency is 0 as well. For CPUs with a known fixed crystal frequency a
quirk list is available to set the frequency,
Kabylake and SkylakeX CPUs are missing in the list of CPUs which need this
quirk. Add them so the TSC frequency can be calculated correctly.
[ tglx: Removed the silly default case as the switch() is only invoked when
cpu_khz is 0. Massaged changelog. ]
Signed-off-by: Prarit Bhargava <prarit@redhat.com>
Cc: Len Brown <len.brown@intel.com>
Cc: Rafael Aquini <aquini@redhat.com>
Cc: "Peter Zijlstra (Intel)" <peterz@infradead.org>
Cc: Andy Lutomirski <luto@kernel.org>
Link: http://lkml.kernel.org/r/1474289501-31717-3-git-send-email-prarit@redhat.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
1396 lines
35 KiB
C
1396 lines
35 KiB
C
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/timer.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/cpufreq.h>
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#include <linux/delay.h>
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#include <linux/clocksource.h>
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#include <linux/percpu.h>
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#include <linux/timex.h>
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#include <linux/static_key.h>
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#include <asm/hpet.h>
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#include <asm/timer.h>
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#include <asm/vgtod.h>
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#include <asm/time.h>
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#include <asm/delay.h>
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#include <asm/hypervisor.h>
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#include <asm/nmi.h>
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#include <asm/x86_init.h>
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#include <asm/geode.h>
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#include <asm/apic.h>
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#include <asm/intel-family.h>
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unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
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EXPORT_SYMBOL(cpu_khz);
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unsigned int __read_mostly tsc_khz;
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EXPORT_SYMBOL(tsc_khz);
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/*
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* TSC can be unstable due to cpufreq or due to unsynced TSCs
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*/
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static int __read_mostly tsc_unstable;
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/* native_sched_clock() is called before tsc_init(), so
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we must start with the TSC soft disabled to prevent
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erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */
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static int __read_mostly tsc_disabled = -1;
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static DEFINE_STATIC_KEY_FALSE(__use_tsc);
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int tsc_clocksource_reliable;
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static u32 art_to_tsc_numerator;
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static u32 art_to_tsc_denominator;
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static u64 art_to_tsc_offset;
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struct clocksource *art_related_clocksource;
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/*
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* Use a ring-buffer like data structure, where a writer advances the head by
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* writing a new data entry and a reader advances the tail when it observes a
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* new entry.
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*
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* Writers are made to wait on readers until there's space to write a new
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* entry.
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*
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* This means that we can always use an {offset, mul} pair to compute a ns
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* value that is 'roughly' in the right direction, even if we're writing a new
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* {offset, mul} pair during the clock read.
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*
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* The down-side is that we can no longer guarantee strict monotonicity anymore
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* (assuming the TSC was that to begin with), because while we compute the
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* intersection point of the two clock slopes and make sure the time is
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* continuous at the point of switching; we can no longer guarantee a reader is
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* strictly before or after the switch point.
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*
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* It does mean a reader no longer needs to disable IRQs in order to avoid
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* CPU-Freq updates messing with his times, and similarly an NMI reader will
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* no longer run the risk of hitting half-written state.
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*/
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struct cyc2ns {
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struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
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struct cyc2ns_data *head; /* 48 + 8 = 56 */
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struct cyc2ns_data *tail; /* 56 + 8 = 64 */
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}; /* exactly fits one cacheline */
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static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
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struct cyc2ns_data *cyc2ns_read_begin(void)
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{
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struct cyc2ns_data *head;
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preempt_disable();
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head = this_cpu_read(cyc2ns.head);
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/*
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* Ensure we observe the entry when we observe the pointer to it.
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* matches the wmb from cyc2ns_write_end().
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*/
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smp_read_barrier_depends();
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head->__count++;
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barrier();
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return head;
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}
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void cyc2ns_read_end(struct cyc2ns_data *head)
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{
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barrier();
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/*
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* If we're the outer most nested read; update the tail pointer
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* when we're done. This notifies possible pending writers
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* that we've observed the head pointer and that the other
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* entry is now free.
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*/
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if (!--head->__count) {
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/*
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* x86-TSO does not reorder writes with older reads;
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* therefore once this write becomes visible to another
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* cpu, we must be finished reading the cyc2ns_data.
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*
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* matches with cyc2ns_write_begin().
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*/
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this_cpu_write(cyc2ns.tail, head);
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}
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preempt_enable();
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}
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/*
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* Begin writing a new @data entry for @cpu.
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*
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* Assumes some sort of write side lock; currently 'provided' by the assumption
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* that cpufreq will call its notifiers sequentially.
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*/
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static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
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{
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struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
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struct cyc2ns_data *data = c2n->data;
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if (data == c2n->head)
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data++;
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/* XXX send an IPI to @cpu in order to guarantee a read? */
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/*
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* When we observe the tail write from cyc2ns_read_end(),
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* the cpu must be done with that entry and its safe
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* to start writing to it.
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*/
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while (c2n->tail == data)
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cpu_relax();
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return data;
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}
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static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
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{
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struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
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/*
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* Ensure the @data writes are visible before we publish the
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* entry. Matches the data-depencency in cyc2ns_read_begin().
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*/
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smp_wmb();
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ACCESS_ONCE(c2n->head) = data;
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}
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/*
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* Accelerators for sched_clock()
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* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george@mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz) / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift. The larger SC is, the more accurate the conversion, but
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* cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
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* (64-bit result) can be used.
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*
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* We can use khz divisor instead of mhz to keep a better precision.
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* (mathieu.desnoyers@polymtl.ca)
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*
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* -johnstul@us.ibm.com "math is hard, lets go shopping!"
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*/
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static void cyc2ns_data_init(struct cyc2ns_data *data)
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{
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data->cyc2ns_mul = 0;
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data->cyc2ns_shift = 0;
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data->cyc2ns_offset = 0;
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data->__count = 0;
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}
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static void cyc2ns_init(int cpu)
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{
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struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
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cyc2ns_data_init(&c2n->data[0]);
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cyc2ns_data_init(&c2n->data[1]);
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c2n->head = c2n->data;
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c2n->tail = c2n->data;
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}
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static inline unsigned long long cycles_2_ns(unsigned long long cyc)
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{
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struct cyc2ns_data *data, *tail;
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unsigned long long ns;
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/*
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* See cyc2ns_read_*() for details; replicated in order to avoid
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* an extra few instructions that came with the abstraction.
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* Notable, it allows us to only do the __count and tail update
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* dance when its actually needed.
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*/
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preempt_disable_notrace();
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data = this_cpu_read(cyc2ns.head);
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tail = this_cpu_read(cyc2ns.tail);
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if (likely(data == tail)) {
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ns = data->cyc2ns_offset;
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ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
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} else {
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data->__count++;
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barrier();
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ns = data->cyc2ns_offset;
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ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, data->cyc2ns_shift);
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barrier();
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if (!--data->__count)
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this_cpu_write(cyc2ns.tail, data);
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}
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preempt_enable_notrace();
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return ns;
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}
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static void set_cyc2ns_scale(unsigned long khz, int cpu)
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{
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unsigned long long tsc_now, ns_now;
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struct cyc2ns_data *data;
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unsigned long flags;
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local_irq_save(flags);
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sched_clock_idle_sleep_event();
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if (!khz)
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goto done;
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data = cyc2ns_write_begin(cpu);
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tsc_now = rdtsc();
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ns_now = cycles_2_ns(tsc_now);
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/*
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* Compute a new multiplier as per the above comment and ensure our
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* time function is continuous; see the comment near struct
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* cyc2ns_data.
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*/
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clocks_calc_mult_shift(&data->cyc2ns_mul, &data->cyc2ns_shift, khz,
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NSEC_PER_MSEC, 0);
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/*
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* cyc2ns_shift is exported via arch_perf_update_userpage() where it is
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* not expected to be greater than 31 due to the original published
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* conversion algorithm shifting a 32-bit value (now specifies a 64-bit
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* value) - refer perf_event_mmap_page documentation in perf_event.h.
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*/
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if (data->cyc2ns_shift == 32) {
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data->cyc2ns_shift = 31;
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data->cyc2ns_mul >>= 1;
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}
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data->cyc2ns_offset = ns_now -
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mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, data->cyc2ns_shift);
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cyc2ns_write_end(cpu, data);
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done:
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sched_clock_idle_wakeup_event(0);
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local_irq_restore(flags);
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}
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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u64 native_sched_clock(void)
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{
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if (static_branch_likely(&__use_tsc)) {
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u64 tsc_now = rdtsc();
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/* return the value in ns */
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return cycles_2_ns(tsc_now);
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}
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/*
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* Fall back to jiffies if there's no TSC available:
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* ( But note that we still use it if the TSC is marked
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* unstable. We do this because unlike Time Of Day,
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* the scheduler clock tolerates small errors and it's
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* very important for it to be as fast as the platform
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* can achieve it. )
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*/
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/* No locking but a rare wrong value is not a big deal: */
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return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
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}
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/*
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* Generate a sched_clock if you already have a TSC value.
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*/
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u64 native_sched_clock_from_tsc(u64 tsc)
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{
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return cycles_2_ns(tsc);
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}
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/* We need to define a real function for sched_clock, to override the
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weak default version */
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#ifdef CONFIG_PARAVIRT
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unsigned long long sched_clock(void)
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{
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return paravirt_sched_clock();
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}
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#else
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unsigned long long
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sched_clock(void) __attribute__((alias("native_sched_clock")));
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#endif
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int check_tsc_unstable(void)
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{
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return tsc_unstable;
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}
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EXPORT_SYMBOL_GPL(check_tsc_unstable);
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#ifdef CONFIG_X86_TSC
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int __init notsc_setup(char *str)
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{
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pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
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tsc_disabled = 1;
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return 1;
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}
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#else
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/*
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* disable flag for tsc. Takes effect by clearing the TSC cpu flag
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* in cpu/common.c
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*/
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int __init notsc_setup(char *str)
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{
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setup_clear_cpu_cap(X86_FEATURE_TSC);
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return 1;
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}
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#endif
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__setup("notsc", notsc_setup);
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static int no_sched_irq_time;
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static int __init tsc_setup(char *str)
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{
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if (!strcmp(str, "reliable"))
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tsc_clocksource_reliable = 1;
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if (!strncmp(str, "noirqtime", 9))
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no_sched_irq_time = 1;
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return 1;
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}
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__setup("tsc=", tsc_setup);
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#define MAX_RETRIES 5
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#define SMI_TRESHOLD 50000
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/*
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* Read TSC and the reference counters. Take care of SMI disturbance
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*/
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static u64 tsc_read_refs(u64 *p, int hpet)
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{
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u64 t1, t2;
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int i;
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for (i = 0; i < MAX_RETRIES; i++) {
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t1 = get_cycles();
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if (hpet)
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*p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
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else
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*p = acpi_pm_read_early();
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t2 = get_cycles();
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if ((t2 - t1) < SMI_TRESHOLD)
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return t2;
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}
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return ULLONG_MAX;
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}
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/*
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* Calculate the TSC frequency from HPET reference
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*/
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static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
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{
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u64 tmp;
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if (hpet2 < hpet1)
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hpet2 += 0x100000000ULL;
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hpet2 -= hpet1;
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tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
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do_div(tmp, 1000000);
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do_div(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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/*
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* Calculate the TSC frequency from PMTimer reference
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*/
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static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
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{
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u64 tmp;
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if (!pm1 && !pm2)
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return ULONG_MAX;
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if (pm2 < pm1)
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pm2 += (u64)ACPI_PM_OVRRUN;
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pm2 -= pm1;
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tmp = pm2 * 1000000000LL;
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do_div(tmp, PMTMR_TICKS_PER_SEC);
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do_div(deltatsc, tmp);
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return (unsigned long) deltatsc;
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}
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#define CAL_MS 10
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#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
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#define CAL_PIT_LOOPS 1000
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#define CAL2_MS 50
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#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
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#define CAL2_PIT_LOOPS 5000
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/*
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* Try to calibrate the TSC against the Programmable
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* Interrupt Timer and return the frequency of the TSC
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* in kHz.
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*
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* Return ULONG_MAX on failure to calibrate.
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*/
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static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
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{
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u64 tsc, t1, t2, delta;
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unsigned long tscmin, tscmax;
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int pitcnt;
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/* Set the Gate high, disable speaker */
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outb((inb(0x61) & ~0x02) | 0x01, 0x61);
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/*
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* Setup CTC channel 2* for mode 0, (interrupt on terminal
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* count mode), binary count. Set the latch register to 50ms
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* (LSB then MSB) to begin countdown.
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*/
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outb(0xb0, 0x43);
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outb(latch & 0xff, 0x42);
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outb(latch >> 8, 0x42);
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tsc = t1 = t2 = get_cycles();
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pitcnt = 0;
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tscmax = 0;
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tscmin = ULONG_MAX;
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while ((inb(0x61) & 0x20) == 0) {
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t2 = get_cycles();
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delta = t2 - tsc;
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tsc = t2;
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if ((unsigned long) delta < tscmin)
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tscmin = (unsigned int) delta;
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if ((unsigned long) delta > tscmax)
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tscmax = (unsigned int) delta;
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pitcnt++;
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}
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/*
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* Sanity checks:
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*
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* If we were not able to read the PIT more than loopmin
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* times, then we have been hit by a massive SMI
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*
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* If the maximum is 10 times larger than the minimum,
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* then we got hit by an SMI as well.
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*/
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if (pitcnt < loopmin || tscmax > 10 * tscmin)
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return ULONG_MAX;
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/* Calculate the PIT value */
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delta = t2 - t1;
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do_div(delta, ms);
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return delta;
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}
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|
|
/*
|
|
* This reads the current MSB of the PIT counter, and
|
|
* checks if we are running on sufficiently fast and
|
|
* non-virtualized hardware.
|
|
*
|
|
* Our expectations are:
|
|
*
|
|
* - the PIT is running at roughly 1.19MHz
|
|
*
|
|
* - each IO is going to take about 1us on real hardware,
|
|
* but we allow it to be much faster (by a factor of 10) or
|
|
* _slightly_ slower (ie we allow up to a 2us read+counter
|
|
* update - anything else implies a unacceptably slow CPU
|
|
* or PIT for the fast calibration to work.
|
|
*
|
|
* - with 256 PIT ticks to read the value, we have 214us to
|
|
* see the same MSB (and overhead like doing a single TSC
|
|
* read per MSB value etc).
|
|
*
|
|
* - We're doing 2 reads per loop (LSB, MSB), and we expect
|
|
* them each to take about a microsecond on real hardware.
|
|
* So we expect a count value of around 100. But we'll be
|
|
* generous, and accept anything over 50.
|
|
*
|
|
* - if the PIT is stuck, and we see *many* more reads, we
|
|
* return early (and the next caller of pit_expect_msb()
|
|
* then consider it a failure when they don't see the
|
|
* next expected value).
|
|
*
|
|
* These expectations mean that we know that we have seen the
|
|
* transition from one expected value to another with a fairly
|
|
* high accuracy, and we didn't miss any events. We can thus
|
|
* use the TSC value at the transitions to calculate a pretty
|
|
* good value for the TSC frequencty.
|
|
*/
|
|
static inline int pit_verify_msb(unsigned char val)
|
|
{
|
|
/* Ignore LSB */
|
|
inb(0x42);
|
|
return inb(0x42) == val;
|
|
}
|
|
|
|
static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
|
|
{
|
|
int count;
|
|
u64 tsc = 0, prev_tsc = 0;
|
|
|
|
for (count = 0; count < 50000; count++) {
|
|
if (!pit_verify_msb(val))
|
|
break;
|
|
prev_tsc = tsc;
|
|
tsc = get_cycles();
|
|
}
|
|
*deltap = get_cycles() - prev_tsc;
|
|
*tscp = tsc;
|
|
|
|
/*
|
|
* We require _some_ success, but the quality control
|
|
* will be based on the error terms on the TSC values.
|
|
*/
|
|
return count > 5;
|
|
}
|
|
|
|
/*
|
|
* How many MSB values do we want to see? We aim for
|
|
* a maximum error rate of 500ppm (in practice the
|
|
* real error is much smaller), but refuse to spend
|
|
* more than 50ms on it.
|
|
*/
|
|
#define MAX_QUICK_PIT_MS 50
|
|
#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
|
|
|
|
static unsigned long quick_pit_calibrate(void)
|
|
{
|
|
int i;
|
|
u64 tsc, delta;
|
|
unsigned long d1, d2;
|
|
|
|
/* Set the Gate high, disable speaker */
|
|
outb((inb(0x61) & ~0x02) | 0x01, 0x61);
|
|
|
|
/*
|
|
* Counter 2, mode 0 (one-shot), binary count
|
|
*
|
|
* NOTE! Mode 2 decrements by two (and then the
|
|
* output is flipped each time, giving the same
|
|
* final output frequency as a decrement-by-one),
|
|
* so mode 0 is much better when looking at the
|
|
* individual counts.
|
|
*/
|
|
outb(0xb0, 0x43);
|
|
|
|
/* Start at 0xffff */
|
|
outb(0xff, 0x42);
|
|
outb(0xff, 0x42);
|
|
|
|
/*
|
|
* The PIT starts counting at the next edge, so we
|
|
* need to delay for a microsecond. The easiest way
|
|
* to do that is to just read back the 16-bit counter
|
|
* once from the PIT.
|
|
*/
|
|
pit_verify_msb(0);
|
|
|
|
if (pit_expect_msb(0xff, &tsc, &d1)) {
|
|
for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
|
|
if (!pit_expect_msb(0xff-i, &delta, &d2))
|
|
break;
|
|
|
|
delta -= tsc;
|
|
|
|
/*
|
|
* Extrapolate the error and fail fast if the error will
|
|
* never be below 500 ppm.
|
|
*/
|
|
if (i == 1 &&
|
|
d1 + d2 >= (delta * MAX_QUICK_PIT_ITERATIONS) >> 11)
|
|
return 0;
|
|
|
|
/*
|
|
* Iterate until the error is less than 500 ppm
|
|
*/
|
|
if (d1+d2 >= delta >> 11)
|
|
continue;
|
|
|
|
/*
|
|
* Check the PIT one more time to verify that
|
|
* all TSC reads were stable wrt the PIT.
|
|
*
|
|
* This also guarantees serialization of the
|
|
* last cycle read ('d2') in pit_expect_msb.
|
|
*/
|
|
if (!pit_verify_msb(0xfe - i))
|
|
break;
|
|
goto success;
|
|
}
|
|
}
|
|
pr_info("Fast TSC calibration failed\n");
|
|
return 0;
|
|
|
|
success:
|
|
/*
|
|
* Ok, if we get here, then we've seen the
|
|
* MSB of the PIT decrement 'i' times, and the
|
|
* error has shrunk to less than 500 ppm.
|
|
*
|
|
* As a result, we can depend on there not being
|
|
* any odd delays anywhere, and the TSC reads are
|
|
* reliable (within the error).
|
|
*
|
|
* kHz = ticks / time-in-seconds / 1000;
|
|
* kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
|
|
* kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
|
|
*/
|
|
delta *= PIT_TICK_RATE;
|
|
do_div(delta, i*256*1000);
|
|
pr_info("Fast TSC calibration using PIT\n");
|
|
return delta;
|
|
}
|
|
|
|
/**
|
|
* native_calibrate_tsc
|
|
* Determine TSC frequency via CPUID, else return 0.
|
|
*/
|
|
unsigned long native_calibrate_tsc(void)
|
|
{
|
|
unsigned int eax_denominator, ebx_numerator, ecx_hz, edx;
|
|
unsigned int crystal_khz;
|
|
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
|
|
return 0;
|
|
|
|
if (boot_cpu_data.cpuid_level < 0x15)
|
|
return 0;
|
|
|
|
eax_denominator = ebx_numerator = ecx_hz = edx = 0;
|
|
|
|
/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */
|
|
cpuid(0x15, &eax_denominator, &ebx_numerator, &ecx_hz, &edx);
|
|
|
|
if (ebx_numerator == 0 || eax_denominator == 0)
|
|
return 0;
|
|
|
|
crystal_khz = ecx_hz / 1000;
|
|
|
|
if (crystal_khz == 0) {
|
|
switch (boot_cpu_data.x86_model) {
|
|
case INTEL_FAM6_SKYLAKE_MOBILE:
|
|
case INTEL_FAM6_SKYLAKE_DESKTOP:
|
|
case INTEL_FAM6_KABYLAKE_MOBILE:
|
|
case INTEL_FAM6_KABYLAKE_DESKTOP:
|
|
crystal_khz = 24000; /* 24.0 MHz */
|
|
break;
|
|
case INTEL_FAM6_SKYLAKE_X:
|
|
crystal_khz = 25000; /* 25.0 MHz */
|
|
break;
|
|
case INTEL_FAM6_ATOM_GOLDMONT:
|
|
crystal_khz = 19200; /* 19.2 MHz */
|
|
break;
|
|
}
|
|
}
|
|
|
|
return crystal_khz * ebx_numerator / eax_denominator;
|
|
}
|
|
|
|
static unsigned long cpu_khz_from_cpuid(void)
|
|
{
|
|
unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx;
|
|
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
|
|
return 0;
|
|
|
|
if (boot_cpu_data.cpuid_level < 0x16)
|
|
return 0;
|
|
|
|
eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0;
|
|
|
|
cpuid(0x16, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx);
|
|
|
|
return eax_base_mhz * 1000;
|
|
}
|
|
|
|
/**
|
|
* native_calibrate_cpu - calibrate the cpu on boot
|
|
*/
|
|
unsigned long native_calibrate_cpu(void)
|
|
{
|
|
u64 tsc1, tsc2, delta, ref1, ref2;
|
|
unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
|
|
unsigned long flags, latch, ms, fast_calibrate;
|
|
int hpet = is_hpet_enabled(), i, loopmin;
|
|
|
|
fast_calibrate = cpu_khz_from_cpuid();
|
|
if (fast_calibrate)
|
|
return fast_calibrate;
|
|
|
|
fast_calibrate = cpu_khz_from_msr();
|
|
if (fast_calibrate)
|
|
return fast_calibrate;
|
|
|
|
local_irq_save(flags);
|
|
fast_calibrate = quick_pit_calibrate();
|
|
local_irq_restore(flags);
|
|
if (fast_calibrate)
|
|
return fast_calibrate;
|
|
|
|
/*
|
|
* Run 5 calibration loops to get the lowest frequency value
|
|
* (the best estimate). We use two different calibration modes
|
|
* here:
|
|
*
|
|
* 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
|
|
* load a timeout of 50ms. We read the time right after we
|
|
* started the timer and wait until the PIT count down reaches
|
|
* zero. In each wait loop iteration we read the TSC and check
|
|
* the delta to the previous read. We keep track of the min
|
|
* and max values of that delta. The delta is mostly defined
|
|
* by the IO time of the PIT access, so we can detect when a
|
|
* SMI/SMM disturbance happened between the two reads. If the
|
|
* maximum time is significantly larger than the minimum time,
|
|
* then we discard the result and have another try.
|
|
*
|
|
* 2) Reference counter. If available we use the HPET or the
|
|
* PMTIMER as a reference to check the sanity of that value.
|
|
* We use separate TSC readouts and check inside of the
|
|
* reference read for a SMI/SMM disturbance. We dicard
|
|
* disturbed values here as well. We do that around the PIT
|
|
* calibration delay loop as we have to wait for a certain
|
|
* amount of time anyway.
|
|
*/
|
|
|
|
/* Preset PIT loop values */
|
|
latch = CAL_LATCH;
|
|
ms = CAL_MS;
|
|
loopmin = CAL_PIT_LOOPS;
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
unsigned long tsc_pit_khz;
|
|
|
|
/*
|
|
* Read the start value and the reference count of
|
|
* hpet/pmtimer when available. Then do the PIT
|
|
* calibration, which will take at least 50ms, and
|
|
* read the end value.
|
|
*/
|
|
local_irq_save(flags);
|
|
tsc1 = tsc_read_refs(&ref1, hpet);
|
|
tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
|
|
tsc2 = tsc_read_refs(&ref2, hpet);
|
|
local_irq_restore(flags);
|
|
|
|
/* Pick the lowest PIT TSC calibration so far */
|
|
tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
|
|
|
|
/* hpet or pmtimer available ? */
|
|
if (ref1 == ref2)
|
|
continue;
|
|
|
|
/* Check, whether the sampling was disturbed by an SMI */
|
|
if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
|
|
continue;
|
|
|
|
tsc2 = (tsc2 - tsc1) * 1000000LL;
|
|
if (hpet)
|
|
tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
|
|
else
|
|
tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
|
|
|
|
tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
|
|
|
|
/* Check the reference deviation */
|
|
delta = ((u64) tsc_pit_min) * 100;
|
|
do_div(delta, tsc_ref_min);
|
|
|
|
/*
|
|
* If both calibration results are inside a 10% window
|
|
* then we can be sure, that the calibration
|
|
* succeeded. We break out of the loop right away. We
|
|
* use the reference value, as it is more precise.
|
|
*/
|
|
if (delta >= 90 && delta <= 110) {
|
|
pr_info("PIT calibration matches %s. %d loops\n",
|
|
hpet ? "HPET" : "PMTIMER", i + 1);
|
|
return tsc_ref_min;
|
|
}
|
|
|
|
/*
|
|
* Check whether PIT failed more than once. This
|
|
* happens in virtualized environments. We need to
|
|
* give the virtual PC a slightly longer timeframe for
|
|
* the HPET/PMTIMER to make the result precise.
|
|
*/
|
|
if (i == 1 && tsc_pit_min == ULONG_MAX) {
|
|
latch = CAL2_LATCH;
|
|
ms = CAL2_MS;
|
|
loopmin = CAL2_PIT_LOOPS;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Now check the results.
|
|
*/
|
|
if (tsc_pit_min == ULONG_MAX) {
|
|
/* PIT gave no useful value */
|
|
pr_warn("Unable to calibrate against PIT\n");
|
|
|
|
/* We don't have an alternative source, disable TSC */
|
|
if (!hpet && !ref1 && !ref2) {
|
|
pr_notice("No reference (HPET/PMTIMER) available\n");
|
|
return 0;
|
|
}
|
|
|
|
/* The alternative source failed as well, disable TSC */
|
|
if (tsc_ref_min == ULONG_MAX) {
|
|
pr_warn("HPET/PMTIMER calibration failed\n");
|
|
return 0;
|
|
}
|
|
|
|
/* Use the alternative source */
|
|
pr_info("using %s reference calibration\n",
|
|
hpet ? "HPET" : "PMTIMER");
|
|
|
|
return tsc_ref_min;
|
|
}
|
|
|
|
/* We don't have an alternative source, use the PIT calibration value */
|
|
if (!hpet && !ref1 && !ref2) {
|
|
pr_info("Using PIT calibration value\n");
|
|
return tsc_pit_min;
|
|
}
|
|
|
|
/* The alternative source failed, use the PIT calibration value */
|
|
if (tsc_ref_min == ULONG_MAX) {
|
|
pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
|
|
return tsc_pit_min;
|
|
}
|
|
|
|
/*
|
|
* The calibration values differ too much. In doubt, we use
|
|
* the PIT value as we know that there are PMTIMERs around
|
|
* running at double speed. At least we let the user know:
|
|
*/
|
|
pr_warn("PIT calibration deviates from %s: %lu %lu\n",
|
|
hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
|
|
pr_info("Using PIT calibration value\n");
|
|
return tsc_pit_min;
|
|
}
|
|
|
|
int recalibrate_cpu_khz(void)
|
|
{
|
|
#ifndef CONFIG_SMP
|
|
unsigned long cpu_khz_old = cpu_khz;
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_TSC))
|
|
return -ENODEV;
|
|
|
|
cpu_khz = x86_platform.calibrate_cpu();
|
|
tsc_khz = x86_platform.calibrate_tsc();
|
|
if (tsc_khz == 0)
|
|
tsc_khz = cpu_khz;
|
|
else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
|
|
cpu_khz = tsc_khz;
|
|
cpu_data(0).loops_per_jiffy = cpufreq_scale(cpu_data(0).loops_per_jiffy,
|
|
cpu_khz_old, cpu_khz);
|
|
|
|
return 0;
|
|
#else
|
|
return -ENODEV;
|
|
#endif
|
|
}
|
|
|
|
EXPORT_SYMBOL(recalibrate_cpu_khz);
|
|
|
|
|
|
static unsigned long long cyc2ns_suspend;
|
|
|
|
void tsc_save_sched_clock_state(void)
|
|
{
|
|
if (!sched_clock_stable())
|
|
return;
|
|
|
|
cyc2ns_suspend = sched_clock();
|
|
}
|
|
|
|
/*
|
|
* Even on processors with invariant TSC, TSC gets reset in some the
|
|
* ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
|
|
* arbitrary value (still sync'd across cpu's) during resume from such sleep
|
|
* states. To cope up with this, recompute the cyc2ns_offset for each cpu so
|
|
* that sched_clock() continues from the point where it was left off during
|
|
* suspend.
|
|
*/
|
|
void tsc_restore_sched_clock_state(void)
|
|
{
|
|
unsigned long long offset;
|
|
unsigned long flags;
|
|
int cpu;
|
|
|
|
if (!sched_clock_stable())
|
|
return;
|
|
|
|
local_irq_save(flags);
|
|
|
|
/*
|
|
* We're coming out of suspend, there's no concurrency yet; don't
|
|
* bother being nice about the RCU stuff, just write to both
|
|
* data fields.
|
|
*/
|
|
|
|
this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
|
|
this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
|
|
|
|
offset = cyc2ns_suspend - sched_clock();
|
|
|
|
for_each_possible_cpu(cpu) {
|
|
per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
|
|
per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
|
|
* changes.
|
|
*
|
|
* RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
|
|
* not that important because current Opteron setups do not support
|
|
* scaling on SMP anyroads.
|
|
*
|
|
* Should fix up last_tsc too. Currently gettimeofday in the
|
|
* first tick after the change will be slightly wrong.
|
|
*/
|
|
|
|
static unsigned int ref_freq;
|
|
static unsigned long loops_per_jiffy_ref;
|
|
static unsigned long tsc_khz_ref;
|
|
|
|
static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
|
|
void *data)
|
|
{
|
|
struct cpufreq_freqs *freq = data;
|
|
unsigned long *lpj;
|
|
|
|
lpj = &boot_cpu_data.loops_per_jiffy;
|
|
#ifdef CONFIG_SMP
|
|
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
|
|
lpj = &cpu_data(freq->cpu).loops_per_jiffy;
|
|
#endif
|
|
|
|
if (!ref_freq) {
|
|
ref_freq = freq->old;
|
|
loops_per_jiffy_ref = *lpj;
|
|
tsc_khz_ref = tsc_khz;
|
|
}
|
|
if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
|
|
(val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
|
|
*lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
|
|
|
|
tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
|
|
if (!(freq->flags & CPUFREQ_CONST_LOOPS))
|
|
mark_tsc_unstable("cpufreq changes");
|
|
|
|
set_cyc2ns_scale(tsc_khz, freq->cpu);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct notifier_block time_cpufreq_notifier_block = {
|
|
.notifier_call = time_cpufreq_notifier
|
|
};
|
|
|
|
static int __init cpufreq_register_tsc_scaling(void)
|
|
{
|
|
if (!boot_cpu_has(X86_FEATURE_TSC))
|
|
return 0;
|
|
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
|
|
return 0;
|
|
cpufreq_register_notifier(&time_cpufreq_notifier_block,
|
|
CPUFREQ_TRANSITION_NOTIFIER);
|
|
return 0;
|
|
}
|
|
|
|
core_initcall(cpufreq_register_tsc_scaling);
|
|
|
|
#endif /* CONFIG_CPU_FREQ */
|
|
|
|
#define ART_CPUID_LEAF (0x15)
|
|
#define ART_MIN_DENOMINATOR (1)
|
|
|
|
|
|
/*
|
|
* If ART is present detect the numerator:denominator to convert to TSC
|
|
*/
|
|
static void detect_art(void)
|
|
{
|
|
unsigned int unused[2];
|
|
|
|
if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
|
|
return;
|
|
|
|
cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator,
|
|
&art_to_tsc_numerator, unused, unused+1);
|
|
|
|
/* Don't enable ART in a VM, non-stop TSC required */
|
|
if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
|
|
!boot_cpu_has(X86_FEATURE_NONSTOP_TSC) ||
|
|
art_to_tsc_denominator < ART_MIN_DENOMINATOR)
|
|
return;
|
|
|
|
if (rdmsrl_safe(MSR_IA32_TSC_ADJUST, &art_to_tsc_offset))
|
|
return;
|
|
|
|
/* Make this sticky over multiple CPU init calls */
|
|
setup_force_cpu_cap(X86_FEATURE_ART);
|
|
}
|
|
|
|
|
|
/* clocksource code */
|
|
|
|
static struct clocksource clocksource_tsc;
|
|
|
|
/*
|
|
* We used to compare the TSC to the cycle_last value in the clocksource
|
|
* structure to avoid a nasty time-warp. This can be observed in a
|
|
* very small window right after one CPU updated cycle_last under
|
|
* xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
|
|
* is smaller than the cycle_last reference value due to a TSC which
|
|
* is slighty behind. This delta is nowhere else observable, but in
|
|
* that case it results in a forward time jump in the range of hours
|
|
* due to the unsigned delta calculation of the time keeping core
|
|
* code, which is necessary to support wrapping clocksources like pm
|
|
* timer.
|
|
*
|
|
* This sanity check is now done in the core timekeeping code.
|
|
* checking the result of read_tsc() - cycle_last for being negative.
|
|
* That works because CLOCKSOURCE_MASK(64) does not mask out any bit.
|
|
*/
|
|
static cycle_t read_tsc(struct clocksource *cs)
|
|
{
|
|
return (cycle_t)rdtsc_ordered();
|
|
}
|
|
|
|
/*
|
|
* .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc()
|
|
*/
|
|
static struct clocksource clocksource_tsc = {
|
|
.name = "tsc",
|
|
.rating = 300,
|
|
.read = read_tsc,
|
|
.mask = CLOCKSOURCE_MASK(64),
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
|
|
CLOCK_SOURCE_MUST_VERIFY,
|
|
.archdata = { .vclock_mode = VCLOCK_TSC },
|
|
};
|
|
|
|
void mark_tsc_unstable(char *reason)
|
|
{
|
|
if (!tsc_unstable) {
|
|
tsc_unstable = 1;
|
|
clear_sched_clock_stable();
|
|
disable_sched_clock_irqtime();
|
|
pr_info("Marking TSC unstable due to %s\n", reason);
|
|
/* Change only the rating, when not registered */
|
|
if (clocksource_tsc.mult)
|
|
clocksource_mark_unstable(&clocksource_tsc);
|
|
else {
|
|
clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
|
|
clocksource_tsc.rating = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(mark_tsc_unstable);
|
|
|
|
static void __init check_system_tsc_reliable(void)
|
|
{
|
|
#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
|
|
if (is_geode_lx()) {
|
|
/* RTSC counts during suspend */
|
|
#define RTSC_SUSP 0x100
|
|
unsigned long res_low, res_high;
|
|
|
|
rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
|
|
/* Geode_LX - the OLPC CPU has a very reliable TSC */
|
|
if (res_low & RTSC_SUSP)
|
|
tsc_clocksource_reliable = 1;
|
|
}
|
|
#endif
|
|
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
|
|
tsc_clocksource_reliable = 1;
|
|
}
|
|
|
|
/*
|
|
* Make an educated guess if the TSC is trustworthy and synchronized
|
|
* over all CPUs.
|
|
*/
|
|
int unsynchronized_tsc(void)
|
|
{
|
|
if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
|
|
return 1;
|
|
|
|
#ifdef CONFIG_SMP
|
|
if (apic_is_clustered_box())
|
|
return 1;
|
|
#endif
|
|
|
|
if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
|
|
return 0;
|
|
|
|
if (tsc_clocksource_reliable)
|
|
return 0;
|
|
/*
|
|
* Intel systems are normally all synchronized.
|
|
* Exceptions must mark TSC as unstable:
|
|
*/
|
|
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
|
|
/* assume multi socket systems are not synchronized: */
|
|
if (num_possible_cpus() > 1)
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Convert ART to TSC given numerator/denominator found in detect_art()
|
|
*/
|
|
struct system_counterval_t convert_art_to_tsc(cycle_t art)
|
|
{
|
|
u64 tmp, res, rem;
|
|
|
|
rem = do_div(art, art_to_tsc_denominator);
|
|
|
|
res = art * art_to_tsc_numerator;
|
|
tmp = rem * art_to_tsc_numerator;
|
|
|
|
do_div(tmp, art_to_tsc_denominator);
|
|
res += tmp + art_to_tsc_offset;
|
|
|
|
return (struct system_counterval_t) {.cs = art_related_clocksource,
|
|
.cycles = res};
|
|
}
|
|
EXPORT_SYMBOL(convert_art_to_tsc);
|
|
|
|
static void tsc_refine_calibration_work(struct work_struct *work);
|
|
static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
|
|
/**
|
|
* tsc_refine_calibration_work - Further refine tsc freq calibration
|
|
* @work - ignored.
|
|
*
|
|
* This functions uses delayed work over a period of a
|
|
* second to further refine the TSC freq value. Since this is
|
|
* timer based, instead of loop based, we don't block the boot
|
|
* process while this longer calibration is done.
|
|
*
|
|
* If there are any calibration anomalies (too many SMIs, etc),
|
|
* or the refined calibration is off by 1% of the fast early
|
|
* calibration, we throw out the new calibration and use the
|
|
* early calibration.
|
|
*/
|
|
static void tsc_refine_calibration_work(struct work_struct *work)
|
|
{
|
|
static u64 tsc_start = -1, ref_start;
|
|
static int hpet;
|
|
u64 tsc_stop, ref_stop, delta;
|
|
unsigned long freq;
|
|
|
|
/* Don't bother refining TSC on unstable systems */
|
|
if (check_tsc_unstable())
|
|
goto out;
|
|
|
|
/*
|
|
* Since the work is started early in boot, we may be
|
|
* delayed the first time we expire. So set the workqueue
|
|
* again once we know timers are working.
|
|
*/
|
|
if (tsc_start == -1) {
|
|
/*
|
|
* Only set hpet once, to avoid mixing hardware
|
|
* if the hpet becomes enabled later.
|
|
*/
|
|
hpet = is_hpet_enabled();
|
|
schedule_delayed_work(&tsc_irqwork, HZ);
|
|
tsc_start = tsc_read_refs(&ref_start, hpet);
|
|
return;
|
|
}
|
|
|
|
tsc_stop = tsc_read_refs(&ref_stop, hpet);
|
|
|
|
/* hpet or pmtimer available ? */
|
|
if (ref_start == ref_stop)
|
|
goto out;
|
|
|
|
/* Check, whether the sampling was disturbed by an SMI */
|
|
if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
|
|
goto out;
|
|
|
|
delta = tsc_stop - tsc_start;
|
|
delta *= 1000000LL;
|
|
if (hpet)
|
|
freq = calc_hpet_ref(delta, ref_start, ref_stop);
|
|
else
|
|
freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
|
|
|
|
/* Make sure we're within 1% */
|
|
if (abs(tsc_khz - freq) > tsc_khz/100)
|
|
goto out;
|
|
|
|
tsc_khz = freq;
|
|
pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
|
|
(unsigned long)tsc_khz / 1000,
|
|
(unsigned long)tsc_khz % 1000);
|
|
|
|
/* Inform the TSC deadline clockevent devices about the recalibration */
|
|
lapic_update_tsc_freq();
|
|
|
|
out:
|
|
if (boot_cpu_has(X86_FEATURE_ART))
|
|
art_related_clocksource = &clocksource_tsc;
|
|
clocksource_register_khz(&clocksource_tsc, tsc_khz);
|
|
}
|
|
|
|
|
|
static int __init init_tsc_clocksource(void)
|
|
{
|
|
if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)
|
|
return 0;
|
|
|
|
if (tsc_clocksource_reliable)
|
|
clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
|
|
/* lower the rating if we already know its unstable: */
|
|
if (check_tsc_unstable()) {
|
|
clocksource_tsc.rating = 0;
|
|
clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
|
|
}
|
|
|
|
if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
|
|
clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
|
|
|
|
/*
|
|
* Trust the results of the earlier calibration on systems
|
|
* exporting a reliable TSC.
|
|
*/
|
|
if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
|
|
clocksource_register_khz(&clocksource_tsc, tsc_khz);
|
|
return 0;
|
|
}
|
|
|
|
schedule_delayed_work(&tsc_irqwork, 0);
|
|
return 0;
|
|
}
|
|
/*
|
|
* We use device_initcall here, to ensure we run after the hpet
|
|
* is fully initialized, which may occur at fs_initcall time.
|
|
*/
|
|
device_initcall(init_tsc_clocksource);
|
|
|
|
void __init tsc_init(void)
|
|
{
|
|
u64 lpj;
|
|
int cpu;
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_TSC)) {
|
|
setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
|
|
return;
|
|
}
|
|
|
|
cpu_khz = x86_platform.calibrate_cpu();
|
|
tsc_khz = x86_platform.calibrate_tsc();
|
|
|
|
/*
|
|
* Trust non-zero tsc_khz as authorative,
|
|
* and use it to sanity check cpu_khz,
|
|
* which will be off if system timer is off.
|
|
*/
|
|
if (tsc_khz == 0)
|
|
tsc_khz = cpu_khz;
|
|
else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
|
|
cpu_khz = tsc_khz;
|
|
|
|
if (!tsc_khz) {
|
|
mark_tsc_unstable("could not calculate TSC khz");
|
|
setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
|
|
return;
|
|
}
|
|
|
|
pr_info("Detected %lu.%03lu MHz processor\n",
|
|
(unsigned long)cpu_khz / 1000,
|
|
(unsigned long)cpu_khz % 1000);
|
|
|
|
/*
|
|
* Secondary CPUs do not run through tsc_init(), so set up
|
|
* all the scale factors for all CPUs, assuming the same
|
|
* speed as the bootup CPU. (cpufreq notifiers will fix this
|
|
* up if their speed diverges)
|
|
*/
|
|
for_each_possible_cpu(cpu) {
|
|
cyc2ns_init(cpu);
|
|
set_cyc2ns_scale(tsc_khz, cpu);
|
|
}
|
|
|
|
if (tsc_disabled > 0)
|
|
return;
|
|
|
|
/* now allow native_sched_clock() to use rdtsc */
|
|
|
|
tsc_disabled = 0;
|
|
static_branch_enable(&__use_tsc);
|
|
|
|
if (!no_sched_irq_time)
|
|
enable_sched_clock_irqtime();
|
|
|
|
lpj = ((u64)tsc_khz * 1000);
|
|
do_div(lpj, HZ);
|
|
lpj_fine = lpj;
|
|
|
|
use_tsc_delay();
|
|
|
|
if (unsynchronized_tsc())
|
|
mark_tsc_unstable("TSCs unsynchronized");
|
|
|
|
check_system_tsc_reliable();
|
|
|
|
detect_art();
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
/*
|
|
* If we have a constant TSC and are using the TSC for the delay loop,
|
|
* we can skip clock calibration if another cpu in the same socket has already
|
|
* been calibrated. This assumes that CONSTANT_TSC applies to all
|
|
* cpus in the socket - this should be a safe assumption.
|
|
*/
|
|
unsigned long calibrate_delay_is_known(void)
|
|
{
|
|
int sibling, cpu = smp_processor_id();
|
|
struct cpumask *mask = topology_core_cpumask(cpu);
|
|
|
|
if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
|
|
return 0;
|
|
|
|
if (!mask)
|
|
return 0;
|
|
|
|
sibling = cpumask_any_but(mask, cpu);
|
|
if (sibling < nr_cpu_ids)
|
|
return cpu_data(sibling).loops_per_jiffy;
|
|
return 0;
|
|
}
|
|
#endif
|