30ad29bb48
Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
/*
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* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <loongson1.h>
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#include <irq.h>
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#define LS1X_INTC_REG(n, x) \
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((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
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#define LS1X_INTC_INTISR(n) LS1X_INTC_REG(n, 0x0)
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#define LS1X_INTC_INTIEN(n) LS1X_INTC_REG(n, 0x4)
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#define LS1X_INTC_INTSET(n) LS1X_INTC_REG(n, 0x8)
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#define LS1X_INTC_INTCLR(n) LS1X_INTC_REG(n, 0xc)
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#define LS1X_INTC_INTPOL(n) LS1X_INTC_REG(n, 0x10)
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#define LS1X_INTC_INTEDGE(n) LS1X_INTC_REG(n, 0x14)
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static void ls1x_irq_ack(struct irq_data *d)
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{
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unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
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unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
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__raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
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| (1 << bit), LS1X_INTC_INTCLR(n));
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}
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static void ls1x_irq_mask(struct irq_data *d)
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{
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unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
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unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
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__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
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& ~(1 << bit), LS1X_INTC_INTIEN(n));
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}
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static void ls1x_irq_mask_ack(struct irq_data *d)
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{
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unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
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unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
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__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
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& ~(1 << bit), LS1X_INTC_INTIEN(n));
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__raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
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| (1 << bit), LS1X_INTC_INTCLR(n));
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}
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static void ls1x_irq_unmask(struct irq_data *d)
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{
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unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
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unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
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__raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
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| (1 << bit), LS1X_INTC_INTIEN(n));
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}
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static struct irq_chip ls1x_irq_chip = {
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.name = "LS1X-INTC",
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.irq_ack = ls1x_irq_ack,
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.irq_mask = ls1x_irq_mask,
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.irq_mask_ack = ls1x_irq_mask_ack,
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.irq_unmask = ls1x_irq_unmask,
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};
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static void ls1x_irq_dispatch(int n)
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{
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u32 int_status, irq;
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/* Get pending sources, masked by current enables */
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int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
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__raw_readl(LS1X_INTC_INTIEN(n));
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if (int_status) {
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irq = LS1X_IRQ(n, __ffs(int_status));
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do_IRQ(irq);
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending;
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pending = read_c0_cause() & read_c0_status() & ST0_IM;
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if (pending & CAUSEF_IP7)
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do_IRQ(TIMER_IRQ);
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else if (pending & CAUSEF_IP2)
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ls1x_irq_dispatch(0); /* INT0 */
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else if (pending & CAUSEF_IP3)
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ls1x_irq_dispatch(1); /* INT1 */
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else if (pending & CAUSEF_IP4)
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ls1x_irq_dispatch(2); /* INT2 */
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else if (pending & CAUSEF_IP5)
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ls1x_irq_dispatch(3); /* INT3 */
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else if (pending & CAUSEF_IP6)
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ls1x_irq_dispatch(4); /* INT4 */
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else
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spurious_interrupt();
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}
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struct irqaction cascade_irqaction = {
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.handler = no_action,
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.name = "cascade",
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.flags = IRQF_NO_THREAD,
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};
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static void __init ls1x_irq_init(int base)
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{
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int n;
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/* Disable interrupts and clear pending,
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* setup all IRQs as high level triggered
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*/
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for (n = 0; n < 4; n++) {
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__raw_writel(0x0, LS1X_INTC_INTIEN(n));
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__raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
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__raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
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/* set DMA0, DMA1 and DMA2 to edge trigger */
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__raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
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}
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for (n = base; n < LS1X_IRQS; n++) {
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irq_set_chip_and_handler(n, &ls1x_irq_chip,
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handle_level_irq);
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}
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setup_irq(INT0_IRQ, &cascade_irqaction);
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setup_irq(INT1_IRQ, &cascade_irqaction);
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setup_irq(INT2_IRQ, &cascade_irqaction);
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setup_irq(INT3_IRQ, &cascade_irqaction);
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}
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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ls1x_irq_init(LS1X_IRQ_BASE);
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}
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