![Markus Elfring](/assets/img/avatar_default.png)
The field "owner" is set by the core. Thus delete an unneeded initialisation. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
540 lines
14 KiB
C
540 lines
14 KiB
C
/*
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* The driver for Freescale MPC512x LocalPlus Bus FIFO
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* (called SCLPC in the Reference Manual).
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*
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* Copyright (C) 2013-2015 Alexander Popov <alex.popov@linux.com>.
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*
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* This file is released under the GPLv2.
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/mpc5121.h>
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#include <asm/io.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-direction.h>
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#include <linux/dma-mapping.h>
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#define DRV_NAME "mpc512x_lpbfifo"
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struct cs_range {
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u32 csnum;
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u32 base; /* must be zero */
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u32 addr;
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u32 size;
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};
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static struct lpbfifo_data {
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spinlock_t lock; /* for protecting lpbfifo_data */
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phys_addr_t regs_phys;
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resource_size_t regs_size;
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struct mpc512x_lpbfifo __iomem *regs;
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int irq;
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struct cs_range *cs_ranges;
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size_t cs_n;
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struct dma_chan *chan;
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struct mpc512x_lpbfifo_request *req;
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dma_addr_t ram_bus_addr;
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bool wait_lpbfifo_irq;
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bool wait_lpbfifo_callback;
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} lpbfifo;
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/*
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* A data transfer from RAM to some device on LPB is finished
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* when both mpc512x_lpbfifo_irq() and mpc512x_lpbfifo_callback()
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* have been called. We execute the callback registered in
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* mpc512x_lpbfifo_request just after that.
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* But for a data transfer from some device on LPB to RAM we don't enable
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* LPBFIFO interrupt because clearing MPC512X_SCLPC_SUCCESS interrupt flag
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* automatically disables LPBFIFO reading request to the DMA controller
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* and the data transfer hangs. So the callback registered in
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* mpc512x_lpbfifo_request is executed at the end of mpc512x_lpbfifo_callback().
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*/
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/*
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* mpc512x_lpbfifo_irq - IRQ handler for LPB FIFO
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*/
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static irqreturn_t mpc512x_lpbfifo_irq(int irq, void *param)
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{
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struct device *dev = (struct device *)param;
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struct mpc512x_lpbfifo_request *req = NULL;
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unsigned long flags;
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u32 status;
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spin_lock_irqsave(&lpbfifo.lock, flags);
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if (!lpbfifo.regs)
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goto end;
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req = lpbfifo.req;
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if (!req || req->dir == MPC512X_LPBFIFO_REQ_DIR_READ) {
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dev_err(dev, "bogus LPBFIFO IRQ\n");
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goto end;
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}
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status = in_be32(&lpbfifo.regs->status);
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if (status != MPC512X_SCLPC_SUCCESS) {
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dev_err(dev, "DMA transfer from RAM to peripheral failed\n");
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out_be32(&lpbfifo.regs->enable,
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MPC512X_SCLPC_RESET | MPC512X_SCLPC_FIFO_RESET);
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goto end;
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}
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/* Clear the interrupt flag */
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out_be32(&lpbfifo.regs->status, MPC512X_SCLPC_SUCCESS);
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lpbfifo.wait_lpbfifo_irq = false;
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if (lpbfifo.wait_lpbfifo_callback)
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goto end;
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/* Transfer is finished, set the FIFO as idle */
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lpbfifo.req = NULL;
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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if (req->callback)
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req->callback(req);
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return IRQ_HANDLED;
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end:
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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return IRQ_HANDLED;
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}
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/*
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* mpc512x_lpbfifo_callback is called by DMA driver when
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* DMA transaction is finished.
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*/
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static void mpc512x_lpbfifo_callback(void *param)
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{
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unsigned long flags;
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struct mpc512x_lpbfifo_request *req = NULL;
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enum dma_data_direction dir;
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spin_lock_irqsave(&lpbfifo.lock, flags);
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if (!lpbfifo.regs) {
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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return;
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}
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req = lpbfifo.req;
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if (!req) {
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pr_err("bogus LPBFIFO callback\n");
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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return;
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}
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/* Release the mapping */
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if (req->dir == MPC512X_LPBFIFO_REQ_DIR_WRITE)
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dir = DMA_TO_DEVICE;
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else
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dir = DMA_FROM_DEVICE;
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dma_unmap_single(lpbfifo.chan->device->dev,
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lpbfifo.ram_bus_addr, req->size, dir);
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lpbfifo.wait_lpbfifo_callback = false;
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if (!lpbfifo.wait_lpbfifo_irq) {
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/* Transfer is finished, set the FIFO as idle */
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lpbfifo.req = NULL;
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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if (req->callback)
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req->callback(req);
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} else {
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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}
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}
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static int mpc512x_lpbfifo_kick(void)
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{
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u32 bits;
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bool no_incr = false;
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u32 bpt = 32; /* max bytes per LPBFIFO transaction involving DMA */
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u32 cs = 0;
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size_t i;
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struct dma_device *dma_dev = NULL;
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struct scatterlist sg;
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enum dma_data_direction dir;
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struct dma_slave_config dma_conf = {};
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struct dma_async_tx_descriptor *dma_tx = NULL;
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dma_cookie_t cookie;
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int ret;
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/*
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* 1. Fit the requirements:
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* - the packet size must be a multiple of 4 since FIFO Data Word
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* Register allows only full-word access according the Reference
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* Manual;
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* - the physical address of the device on LPB and the packet size
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* must be aligned on BPT (bytes per transaction) or 8-bytes
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* boundary according the Reference Manual;
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* - but we choose DMA maxburst equal (or very close to) BPT to prevent
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* DMA controller from overtaking FIFO and causing FIFO underflow
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* error. So we force the packet size to be aligned on BPT boundary
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* not to confuse DMA driver which requires the packet size to be
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* aligned on maxburst boundary;
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* - BPT should be set to the LPB device port size for operation with
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* disabled auto-incrementing according Reference Manual.
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*/
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if (lpbfifo.req->size == 0 || !IS_ALIGNED(lpbfifo.req->size, 4))
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return -EINVAL;
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if (lpbfifo.req->portsize != LPB_DEV_PORTSIZE_UNDEFINED) {
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bpt = lpbfifo.req->portsize;
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no_incr = true;
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}
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while (bpt > 1) {
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if (IS_ALIGNED(lpbfifo.req->dev_phys_addr, min(bpt, 0x8u)) &&
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IS_ALIGNED(lpbfifo.req->size, bpt)) {
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break;
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}
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if (no_incr)
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return -EINVAL;
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bpt >>= 1;
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}
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dma_conf.dst_maxburst = max(bpt, 0x4u) / 4;
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dma_conf.src_maxburst = max(bpt, 0x4u) / 4;
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for (i = 0; i < lpbfifo.cs_n; i++) {
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phys_addr_t cs_start = lpbfifo.cs_ranges[i].addr;
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phys_addr_t cs_end = cs_start + lpbfifo.cs_ranges[i].size;
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phys_addr_t access_start = lpbfifo.req->dev_phys_addr;
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phys_addr_t access_end = access_start + lpbfifo.req->size;
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if (access_start >= cs_start && access_end <= cs_end) {
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cs = lpbfifo.cs_ranges[i].csnum;
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break;
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}
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}
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if (i == lpbfifo.cs_n)
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return -EFAULT;
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/* 2. Prepare DMA */
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dma_dev = lpbfifo.chan->device;
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if (lpbfifo.req->dir == MPC512X_LPBFIFO_REQ_DIR_WRITE) {
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dir = DMA_TO_DEVICE;
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dma_conf.direction = DMA_MEM_TO_DEV;
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dma_conf.dst_addr = lpbfifo.regs_phys +
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offsetof(struct mpc512x_lpbfifo, data_word);
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} else {
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dir = DMA_FROM_DEVICE;
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dma_conf.direction = DMA_DEV_TO_MEM;
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dma_conf.src_addr = lpbfifo.regs_phys +
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offsetof(struct mpc512x_lpbfifo, data_word);
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}
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dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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/* Make DMA channel work with LPB FIFO data register */
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if (dma_dev->device_config(lpbfifo.chan, &dma_conf)) {
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ret = -EINVAL;
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goto err_dma_prep;
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}
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sg_init_table(&sg, 1);
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sg_dma_address(&sg) = dma_map_single(dma_dev->dev,
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lpbfifo.req->ram_virt_addr, lpbfifo.req->size, dir);
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if (dma_mapping_error(dma_dev->dev, sg_dma_address(&sg)))
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return -EFAULT;
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lpbfifo.ram_bus_addr = sg_dma_address(&sg); /* For freeing later */
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sg_dma_len(&sg) = lpbfifo.req->size;
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dma_tx = dmaengine_prep_slave_sg(lpbfifo.chan, &sg,
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1, dma_conf.direction, 0);
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if (!dma_tx) {
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ret = -ENOSPC;
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goto err_dma_prep;
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}
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dma_tx->callback = mpc512x_lpbfifo_callback;
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dma_tx->callback_param = NULL;
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/* 3. Prepare FIFO */
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out_be32(&lpbfifo.regs->enable,
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MPC512X_SCLPC_RESET | MPC512X_SCLPC_FIFO_RESET);
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out_be32(&lpbfifo.regs->enable, 0x0);
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/*
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* Configure the watermarks for write operation (RAM->DMA->FIFO->dev):
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* - high watermark 7 words according the Reference Manual,
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* - low watermark 512 bytes (half of the FIFO).
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* These watermarks don't work for read operation since the
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* MPC512X_SCLPC_FLUSH bit is set (according the Reference Manual).
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*/
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out_be32(&lpbfifo.regs->fifo_ctrl, MPC512X_SCLPC_FIFO_CTRL(0x7));
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out_be32(&lpbfifo.regs->fifo_alarm, MPC512X_SCLPC_FIFO_ALARM(0x200));
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/*
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* Start address is a physical address of the region which belongs
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* to the device on the LocalPlus Bus
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*/
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out_be32(&lpbfifo.regs->start_addr, lpbfifo.req->dev_phys_addr);
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/*
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* Configure chip select, transfer direction, address increment option
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* and bytes per transaction option
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*/
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bits = MPC512X_SCLPC_CS(cs);
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if (lpbfifo.req->dir == MPC512X_LPBFIFO_REQ_DIR_READ)
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bits |= MPC512X_SCLPC_READ | MPC512X_SCLPC_FLUSH;
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if (no_incr)
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bits |= MPC512X_SCLPC_DAI;
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bits |= MPC512X_SCLPC_BPT(bpt);
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out_be32(&lpbfifo.regs->ctrl, bits);
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/* Unmask irqs */
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bits = MPC512X_SCLPC_ENABLE | MPC512X_SCLPC_ABORT_INT_ENABLE;
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if (lpbfifo.req->dir == MPC512X_LPBFIFO_REQ_DIR_WRITE)
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bits |= MPC512X_SCLPC_NORM_INT_ENABLE;
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else
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lpbfifo.wait_lpbfifo_irq = false;
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out_be32(&lpbfifo.regs->enable, bits);
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/* 4. Set packet size and kick FIFO off */
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bits = lpbfifo.req->size | MPC512X_SCLPC_START;
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out_be32(&lpbfifo.regs->pkt_size, bits);
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/* 5. Finally kick DMA off */
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cookie = dma_tx->tx_submit(dma_tx);
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if (dma_submit_error(cookie)) {
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ret = -ENOSPC;
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goto err_dma_submit;
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}
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return 0;
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err_dma_submit:
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out_be32(&lpbfifo.regs->enable,
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MPC512X_SCLPC_RESET | MPC512X_SCLPC_FIFO_RESET);
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err_dma_prep:
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dma_unmap_single(dma_dev->dev, sg_dma_address(&sg),
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lpbfifo.req->size, dir);
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return ret;
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}
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static int mpc512x_lpbfifo_submit_locked(struct mpc512x_lpbfifo_request *req)
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{
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int ret = 0;
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if (!lpbfifo.regs)
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return -ENODEV;
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/* Check whether a transfer is in progress */
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if (lpbfifo.req)
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return -EBUSY;
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lpbfifo.wait_lpbfifo_irq = true;
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lpbfifo.wait_lpbfifo_callback = true;
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lpbfifo.req = req;
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ret = mpc512x_lpbfifo_kick();
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if (ret != 0)
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lpbfifo.req = NULL; /* Set the FIFO as idle */
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return ret;
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}
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int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req)
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{
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&lpbfifo.lock, flags);
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ret = mpc512x_lpbfifo_submit_locked(req);
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spin_unlock_irqrestore(&lpbfifo.lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(mpc512x_lpbfifo_submit);
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/*
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* LPBFIFO driver uses "ranges" property of "localbus" device tree node
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* for being able to determine the chip select number of a client device
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* ordering a DMA transfer.
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*/
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static int get_cs_ranges(struct device *dev)
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{
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int ret = -ENODEV;
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struct device_node *lb_node;
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const u32 *addr_cells_p;
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const u32 *size_cells_p;
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int proplen;
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size_t i;
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lb_node = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-localbus");
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if (!lb_node)
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return ret;
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/*
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* The node defined as compatible with 'fsl,mpc5121-localbus'
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* should have two address cells and one size cell.
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* Every item of its ranges property should consist of:
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* - the first address cell which is the chipselect number;
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* - the second address cell which is the offset in the chipselect,
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* must be zero.
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* - CPU address of the beginning of an access window;
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* - the only size cell which is the size of an access window.
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*/
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addr_cells_p = of_get_property(lb_node, "#address-cells", NULL);
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size_cells_p = of_get_property(lb_node, "#size-cells", NULL);
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if (addr_cells_p == NULL || *addr_cells_p != 2 ||
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size_cells_p == NULL || *size_cells_p != 1) {
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goto end;
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}
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proplen = of_property_count_u32_elems(lb_node, "ranges");
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if (proplen <= 0 || proplen % 4 != 0)
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goto end;
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lpbfifo.cs_n = proplen / 4;
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lpbfifo.cs_ranges = devm_kcalloc(dev, lpbfifo.cs_n,
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sizeof(struct cs_range), GFP_KERNEL);
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if (!lpbfifo.cs_ranges)
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goto end;
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if (of_property_read_u32_array(lb_node, "ranges",
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(u32 *)lpbfifo.cs_ranges, proplen) != 0) {
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goto end;
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}
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for (i = 0; i < lpbfifo.cs_n; i++) {
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if (lpbfifo.cs_ranges[i].base != 0)
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goto end;
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}
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ret = 0;
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end:
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of_node_put(lb_node);
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return ret;
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}
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static int mpc512x_lpbfifo_probe(struct platform_device *pdev)
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{
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struct resource r;
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int ret = 0;
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memset(&lpbfifo, 0, sizeof(struct lpbfifo_data));
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spin_lock_init(&lpbfifo.lock);
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lpbfifo.chan = dma_request_slave_channel(&pdev->dev, "rx-tx");
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if (lpbfifo.chan == NULL)
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return -EPROBE_DEFER;
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if (of_address_to_resource(pdev->dev.of_node, 0, &r) != 0) {
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dev_err(&pdev->dev, "bad 'reg' in 'sclpc' device tree node\n");
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ret = -ENODEV;
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goto err0;
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}
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lpbfifo.regs_phys = r.start;
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lpbfifo.regs_size = resource_size(&r);
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if (!devm_request_mem_region(&pdev->dev, lpbfifo.regs_phys,
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lpbfifo.regs_size, DRV_NAME)) {
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dev_err(&pdev->dev, "unable to request region\n");
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ret = -EBUSY;
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goto err0;
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}
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lpbfifo.regs = devm_ioremap(&pdev->dev,
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lpbfifo.regs_phys, lpbfifo.regs_size);
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if (!lpbfifo.regs) {
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dev_err(&pdev->dev, "mapping registers failed\n");
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ret = -ENOMEM;
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goto err0;
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}
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out_be32(&lpbfifo.regs->enable,
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MPC512X_SCLPC_RESET | MPC512X_SCLPC_FIFO_RESET);
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if (get_cs_ranges(&pdev->dev) != 0) {
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dev_err(&pdev->dev, "bad '/localbus' device tree node\n");
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ret = -ENODEV;
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goto err0;
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}
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lpbfifo.irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
|
|
if (lpbfifo.irq == NO_IRQ) {
|
|
dev_err(&pdev->dev, "mapping irq failed\n");
|
|
ret = -ENODEV;
|
|
goto err0;
|
|
}
|
|
|
|
if (request_irq(lpbfifo.irq, mpc512x_lpbfifo_irq, 0,
|
|
DRV_NAME, &pdev->dev) != 0) {
|
|
dev_err(&pdev->dev, "requesting irq failed\n");
|
|
ret = -ENODEV;
|
|
goto err1;
|
|
}
|
|
|
|
dev_info(&pdev->dev, "probe succeeded\n");
|
|
return 0;
|
|
|
|
err1:
|
|
irq_dispose_mapping(lpbfifo.irq);
|
|
err0:
|
|
dma_release_channel(lpbfifo.chan);
|
|
return ret;
|
|
}
|
|
|
|
static int mpc512x_lpbfifo_remove(struct platform_device *pdev)
|
|
{
|
|
unsigned long flags;
|
|
struct dma_device *dma_dev = lpbfifo.chan->device;
|
|
struct mpc512x_lpbfifo __iomem *regs = NULL;
|
|
|
|
spin_lock_irqsave(&lpbfifo.lock, flags);
|
|
regs = lpbfifo.regs;
|
|
lpbfifo.regs = NULL;
|
|
spin_unlock_irqrestore(&lpbfifo.lock, flags);
|
|
|
|
dma_dev->device_terminate_all(lpbfifo.chan);
|
|
out_be32(®s->enable, MPC512X_SCLPC_RESET | MPC512X_SCLPC_FIFO_RESET);
|
|
|
|
free_irq(lpbfifo.irq, &pdev->dev);
|
|
irq_dispose_mapping(lpbfifo.irq);
|
|
dma_release_channel(lpbfifo.chan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mpc512x_lpbfifo_match[] = {
|
|
{ .compatible = "fsl,mpc512x-lpbfifo", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mpc512x_lpbfifo_match);
|
|
|
|
static struct platform_driver mpc512x_lpbfifo_driver = {
|
|
.probe = mpc512x_lpbfifo_probe,
|
|
.remove = mpc512x_lpbfifo_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = mpc512x_lpbfifo_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mpc512x_lpbfifo_driver);
|
|
|
|
MODULE_AUTHOR("Alexander Popov <alex.popov@linux.com>");
|
|
MODULE_DESCRIPTION("MPC512x LocalPlus Bus FIFO device driver");
|
|
MODULE_LICENSE("GPL v2");
|