![Benjamin Herrenschmidt](/assets/img/avatar_default.png)
This converts all the 32-bit platforms to use the expanded device-tree which is a pretty mechanical change. Unlike 64-bit, the 32-bit kernel didn't rely on platform initializations to setup the MMU since it sets it up entirely before probe_machine() so the move has comparatively less consequences though it's a bigger patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
575 lines
15 KiB
C
575 lines
15 KiB
C
/*
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* P1022DS board specific routines
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*
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* Authors: Travis Wheatley <travis.wheatley@freescale.com>
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* Dave Liu <daveliu@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This file is taken from the Freescale P1022DS BSP, with modifications:
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* 2) No AMP support
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* 3) No PCI endpoint support
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/fsl/guts.h>
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <asm/div64.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/udbg.h>
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#include <asm/fsl_lbc.h>
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#include "smp.h"
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#include "mpc85xx.h"
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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#define PMUXCR_ELBCDIU_MASK 0xc0000000
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#define PMUXCR_ELBCDIU_NOR16 0x80000000
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#define PMUXCR_ELBCDIU_DIU 0x40000000
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/*
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* Board-specific initialization of the DIU. This code should probably be
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* executed when the DIU is opened, rather than in arch code, but the DIU
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* driver does not have a mechanism for this (yet).
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*
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* This is especially problematic on the P1022DS because the local bus (eLBC)
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* and the DIU video signals share the same pins, which means that enabling the
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* DIU will disable access to NOR flash.
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*/
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
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/* Some ngPIXIS register definitions */
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#define PX_CTL 3
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#define PX_BRDCFG0 8
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#define PX_BRDCFG1 9
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#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
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#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
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#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
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#define PX_BRDCFG0_ELBC_DIU 0x02
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#define PX_BRDCFG1_DVIEN 0x80
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#define PX_BRDCFG1_DFPEN 0x40
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#define PX_BRDCFG1_BACKLIGHT 0x20
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#define PX_BRDCFG1_DDCEN 0x10
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#define PX_CTL_ALTACC 0x80
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_MASK 0x0E000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_MASK 0x01800000
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_MASK 0x00600000
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_MASK 0x00180000
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#define AD_RED_C_SHIFT 19
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#define AD_PALETTE 0x00040000
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#define AD_PIXEL_S_MASK 0x00030000
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_MASK 0x0000F000
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_MASK 0x00000F00
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_MASK 0x000000F0
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_MASK 0x0000000F
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#define AD_COMP_0_SHIFT 0
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#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
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cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
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(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
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(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
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(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
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(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
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struct fsl_law {
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u32 lawbar;
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u32 reserved1;
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u32 lawar;
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u32 reserved[5];
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};
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#define LAWBAR_MASK 0x00F00000
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#define LAWBAR_SHIFT 12
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#define LAWAR_EN 0x80000000
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#define LAWAR_TGT_MASK 0x01F00000
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#define LAW_TRGT_IF_LBC (0x04 << 20)
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#define LAWAR_MASK (LAWAR_EN | LAWAR_TGT_MASK)
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#define LAWAR_MATCH (LAWAR_EN | LAW_TRGT_IF_LBC)
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#define BR_BA 0xFFFF8000
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/*
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* Map a BRx value to a physical address
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*
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* The localbus BRx registers only store the lower 32 bits of the address. To
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* obtain the upper four bits, we need to scan the LAW table. The entry which
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* maps to the localbus will contain the upper four bits.
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*/
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static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
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{
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#ifndef CONFIG_PHYS_64BIT
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/*
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* If we only have 32-bit addressing, then the BRx address *is* the
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* physical address.
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*/
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return br & BR_BA;
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#else
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const struct fsl_law *law = ecm + 0xc08;
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unsigned int i;
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for (i = 0; i < count; i++) {
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u64 lawbar = in_be32(&law[i].lawbar);
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u32 lawar = in_be32(&law[i].lawar);
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if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
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/* Extract the upper four bits */
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return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
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}
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return 0;
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#endif
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}
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/**
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* p1022ds_set_monitor_port: switch the output to a different monitor port
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*/
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static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
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{
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struct device_node *guts_node;
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struct device_node *lbc_node = NULL;
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struct device_node *law_node = NULL;
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struct ccsr_guts __iomem *guts;
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struct fsl_lbc_regs *lbc = NULL;
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void *ecm = NULL;
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u8 __iomem *lbc_lcs0_ba = NULL;
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u8 __iomem *lbc_lcs1_ba = NULL;
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phys_addr_t cs0_addr, cs1_addr;
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u32 br0, or0, br1, or1;
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const __be32 *iprop;
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unsigned int num_laws;
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u8 b;
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/* Map the global utilities registers. */
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guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_node) {
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pr_err("p1022ds: missing global utilities device node\n");
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return;
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}
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guts = of_iomap(guts_node, 0);
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if (!guts) {
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pr_err("p1022ds: could not map global utilities device\n");
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goto exit;
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}
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lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
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if (!lbc_node) {
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pr_err("p1022ds: missing localbus node\n");
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goto exit;
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}
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lbc = of_iomap(lbc_node, 0);
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if (!lbc) {
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pr_err("p1022ds: could not map localbus node\n");
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goto exit;
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}
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law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
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if (!law_node) {
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pr_err("p1022ds: missing local access window node\n");
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goto exit;
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}
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ecm = of_iomap(law_node, 0);
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if (!ecm) {
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pr_err("p1022ds: could not map local access window node\n");
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goto exit;
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}
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iprop = of_get_property(law_node, "fsl,num-laws", NULL);
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if (!iprop) {
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pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
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goto exit;
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}
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num_laws = be32_to_cpup(iprop);
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/*
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* Indirect mode requires both BR0 and BR1 to be set to "GPCM",
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* otherwise writes to these addresses won't actually appear on the
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* local bus, and so the PIXIS won't see them.
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*
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* In FCM mode, writes go to the NAND controller, which does not pass
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* them to the localbus directly. So we force BR0 and BR1 into GPCM
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* mode, since we don't care about what's behind the localbus any
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* more.
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*/
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br0 = in_be32(&lbc->bank[0].br);
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br1 = in_be32(&lbc->bank[1].br);
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or0 = in_be32(&lbc->bank[0].or);
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or1 = in_be32(&lbc->bank[1].or);
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/* Make sure CS0 and CS1 are programmed */
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if (!(br0 & BR_V) || !(br1 & BR_V)) {
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pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
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goto exit;
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}
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/*
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* Use the existing BRx/ORx values if it's already GPCM. Otherwise,
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* force the values to simple 32KB GPCM windows with the most
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* conservative timing.
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*/
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if ((br0 & BR_MSEL) != BR_MS_GPCM) {
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br0 = (br0 & BR_BA) | BR_V;
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or0 = 0xFFFF8000 | 0xFF7;
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out_be32(&lbc->bank[0].br, br0);
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out_be32(&lbc->bank[0].or, or0);
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}
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if ((br1 & BR_MSEL) != BR_MS_GPCM) {
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br1 = (br1 & BR_BA) | BR_V;
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or1 = 0xFFFF8000 | 0xFF7;
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out_be32(&lbc->bank[1].br, br1);
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out_be32(&lbc->bank[1].or, or1);
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}
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cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
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if (!cs0_addr) {
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pr_err("p1022ds: could not determine physical address for CS0"
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" (BR0=%08x)\n", br0);
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goto exit;
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}
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cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
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if (!cs1_addr) {
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pr_err("p1022ds: could not determine physical address for CS1"
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" (BR1=%08x)\n", br1);
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goto exit;
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}
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lbc_lcs0_ba = ioremap(cs0_addr, 1);
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if (!lbc_lcs0_ba) {
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pr_err("p1022ds: could not ioremap CS0 address %llx\n",
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(unsigned long long)cs0_addr);
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goto exit;
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}
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lbc_lcs1_ba = ioremap(cs1_addr, 1);
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if (!lbc_lcs1_ba) {
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pr_err("p1022ds: could not ioremap CS1 address %llx\n",
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(unsigned long long)cs1_addr);
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goto exit;
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}
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/* Make sure we're in indirect mode first. */
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if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
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PMUXCR_ELBCDIU_DIU) {
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struct device_node *pixis_node;
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void __iomem *pixis;
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pixis_node =
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of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
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if (!pixis_node) {
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pr_err("p1022ds: missing pixis node\n");
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goto exit;
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}
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pixis = of_iomap(pixis_node, 0);
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of_node_put(pixis_node);
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if (!pixis) {
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pr_err("p1022ds: could not map pixis registers\n");
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goto exit;
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}
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/* Enable indirect PIXIS mode. */
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setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
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iounmap(pixis);
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/* Switch the board mux to the DIU */
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out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
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b = in_8(lbc_lcs1_ba);
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b |= PX_BRDCFG0_ELBC_DIU;
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out_8(lbc_lcs1_ba, b);
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/* Set the chip mux to DIU mode. */
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clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
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PMUXCR_ELBCDIU_DIU);
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in_be32(&guts->pmuxcr);
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}
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switch (port) {
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case FSL_DIU_PORT_DVI:
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/* Enable the DVI port, disable the DFP and the backlight */
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out_8(lbc_lcs0_ba, PX_BRDCFG1);
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b = in_8(lbc_lcs1_ba);
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b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
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b |= PX_BRDCFG1_DVIEN;
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out_8(lbc_lcs1_ba, b);
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break;
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case FSL_DIU_PORT_LVDS:
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/*
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* LVDS also needs backlight enabled, otherwise the display
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* will be blank.
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*/
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/* Enable the DFP port, disable the DVI and the backlight */
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out_8(lbc_lcs0_ba, PX_BRDCFG1);
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b = in_8(lbc_lcs1_ba);
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b &= ~PX_BRDCFG1_DVIEN;
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b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
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out_8(lbc_lcs1_ba, b);
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break;
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default:
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pr_err("p1022ds: unsupported monitor port %i\n", port);
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}
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exit:
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if (lbc_lcs1_ba)
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iounmap(lbc_lcs1_ba);
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if (lbc_lcs0_ba)
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iounmap(lbc_lcs0_ba);
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if (lbc)
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iounmap(lbc);
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if (ecm)
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iounmap(ecm);
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if (guts)
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iounmap(guts);
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of_node_put(law_node);
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of_node_put(lbc_node);
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of_node_put(guts_node);
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}
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/**
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* p1022ds_set_pixel_clock: program the DIU's clock
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*
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* @pixclock: the wavelength, in picoseconds, of the clock
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*/
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void p1022ds_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *guts_np = NULL;
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struct ccsr_guts __iomem *guts;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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/* Map the global utilities registers. */
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_np) {
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pr_err("p1022ds: missing global utilities device node\n");
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return;
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}
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guts = of_iomap(guts_np, 0);
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of_node_put(guts_np);
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if (!guts) {
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pr_err("p1022ds: could not map global utilities device\n");
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return;
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}
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/* Convert pixclock from a wavelength to a frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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/*
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* 'pxclk' is the ratio of the platform clock to the pixel clock.
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* This number is programmed into the CLKDVDR register, and the valid
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* range of values is 2-255.
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*/
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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pxclk = clamp_t(u32, pxclk, 2, 255);
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(&guts->clkdvdr,
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
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iounmap(guts);
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}
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/**
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* p1022ds_valid_monitor_port: set the monitor port for sysfs
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*/
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enum fsl_diu_monitor_port
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p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
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{
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switch (port) {
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case FSL_DIU_PORT_DVI:
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case FSL_DIU_PORT_LVDS:
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return port;
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default:
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return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
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}
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}
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#endif
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void __init p1022_ds_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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/* TRUE if there is a "video=fslfb" command-line parameter. */
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static bool fslfb;
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/*
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* Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
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* true if we find it.
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*
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* We need to use early_param() instead of __setup() because the normal
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* __setup() gets called to late. However, early_param() gets called very
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* early, before the device tree is unflattened, so all we can do now is set a
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* global variable. Later on, p1022_ds_setup_arch() will use that variable
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* to determine if we need to update the device tree.
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*/
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static int __init early_video_setup(char *options)
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{
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fslfb = (strncmp(options, "fslfb:", 6) == 0);
|
|
|
|
return 0;
|
|
}
|
|
early_param("video", early_video_setup);
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Setup the architecture
|
|
*/
|
|
static void __init p1022_ds_setup_arch(void)
|
|
{
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("p1022_ds_setup_arch()", 0);
|
|
|
|
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
|
|
diu_ops.set_monitor_port = p1022ds_set_monitor_port;
|
|
diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
|
|
diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
|
|
|
|
/*
|
|
* Disable the NOR and NAND flash nodes if there is video=fslfb...
|
|
* command-line parameter. When the DIU is active, the localbus is
|
|
* unavailable, so we have to disable these nodes before the MTD
|
|
* driver loads.
|
|
*/
|
|
if (fslfb) {
|
|
struct device_node *np =
|
|
of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
|
|
|
|
if (np) {
|
|
struct device_node *np2;
|
|
|
|
of_node_get(np);
|
|
np2 = of_find_compatible_node(np, NULL, "cfi-flash");
|
|
if (np2) {
|
|
static struct property nor_status = {
|
|
.name = "status",
|
|
.value = "disabled",
|
|
.length = sizeof("disabled"),
|
|
};
|
|
|
|
/*
|
|
* of_update_property() is called before
|
|
* kmalloc() is available, so the 'new' object
|
|
* should be allocated in the global area.
|
|
* The easiest way is to do that is to
|
|
* allocate one static local variable for each
|
|
* call to this function.
|
|
*/
|
|
pr_info("p1022ds: disabling %s node",
|
|
np2->full_name);
|
|
of_update_property(np2, &nor_status);
|
|
of_node_put(np2);
|
|
}
|
|
|
|
of_node_get(np);
|
|
np2 = of_find_compatible_node(np, NULL,
|
|
"fsl,elbc-fcm-nand");
|
|
if (np2) {
|
|
static struct property nand_status = {
|
|
.name = "status",
|
|
.value = "disabled",
|
|
.length = sizeof("disabled"),
|
|
};
|
|
|
|
pr_info("p1022ds: disabling %s node",
|
|
np2->full_name);
|
|
of_update_property(np2, &nand_status);
|
|
of_node_put(np2);
|
|
}
|
|
|
|
of_node_put(np);
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
mpc85xx_smp_init();
|
|
|
|
fsl_pci_assign_primary();
|
|
|
|
swiotlb_detect_4g();
|
|
|
|
pr_info("Freescale P1022 DS reference board\n");
|
|
}
|
|
|
|
machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
|
|
|
|
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
|
|
|
|
/*
|
|
* Called very early, device-tree isn't unflattened
|
|
*/
|
|
static int __init p1022_ds_probe(void)
|
|
{
|
|
return of_machine_is_compatible("fsl,p1022ds");
|
|
}
|
|
|
|
define_machine(p1022_ds) {
|
|
.name = "P1022 DS",
|
|
.probe = p1022_ds_probe,
|
|
.setup_arch = p1022_ds_setup_arch,
|
|
.init_IRQ = p1022_ds_pic_init,
|
|
#ifdef CONFIG_PCI
|
|
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
|
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
|
|
#endif
|
|
.get_irq = mpic_get_irq,
|
|
.restart = fsl_rstcr_restart,
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
.progress = udbg_progress,
|
|
};
|