![Thomas Gleixner](/assets/img/avatar_default.png)
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
414 lines
11 KiB
C
414 lines
11 KiB
C
/*
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* Cell Internal Interrupt Controller
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*
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* Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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* IBM, Corp.
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*
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* (C) Copyright IBM Deutschland Entwicklung GmbH 2005
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*
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* Author: Arnd Bergmann <arndb@de.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* TODO:
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* - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
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* vs node numbers in the setup code
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* - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
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* a non-active node to the active node)
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/export.h>
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#include <linux/percpu.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/kernel_stat.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/prom.h>
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#include <asm/ptrace.h>
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#include <asm/machdep.h>
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#include <asm/cell-regs.h>
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#include "interrupt.h"
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struct iic {
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struct cbe_iic_thread_regs __iomem *regs;
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u8 target_id;
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u8 eoi_stack[16];
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int eoi_ptr;
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struct device_node *node;
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};
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static DEFINE_PER_CPU(struct iic, cpu_iic);
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#define IIC_NODE_COUNT 2
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static struct irq_domain *iic_host;
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/* Convert between "pending" bits and hw irq number */
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static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
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{
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unsigned char unit = bits.source & 0xf;
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unsigned char node = bits.source >> 4;
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unsigned char class = bits.class & 3;
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/* Decode IPIs */
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if (bits.flags & CBE_IIC_IRQ_IPI)
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return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
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else
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return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
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}
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static void iic_mask(struct irq_data *d)
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{
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}
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static void iic_unmask(struct irq_data *d)
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{
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}
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static void iic_eoi(struct irq_data *d)
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{
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struct iic *iic = this_cpu_ptr(&cpu_iic);
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out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
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BUG_ON(iic->eoi_ptr < 0);
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}
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static struct irq_chip iic_chip = {
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.name = "CELL-IIC",
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.irq_mask = iic_mask,
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.irq_unmask = iic_unmask,
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.irq_eoi = iic_eoi,
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};
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static void iic_ioexc_eoi(struct irq_data *d)
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{
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}
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static void iic_ioexc_cascade(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct cbe_iic_regs __iomem *node_iic =
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(void __iomem *)irq_desc_get_handler_data(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
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unsigned long bits, ack;
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int cascade;
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for (;;) {
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bits = in_be64(&node_iic->iic_is);
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if (bits == 0)
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break;
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/* pre-ack edge interrupts */
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ack = bits & IIC_ISR_EDGE_MASK;
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if (ack)
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out_be64(&node_iic->iic_is, ack);
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/* handle them */
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for (cascade = 63; cascade >= 0; cascade--)
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if (bits & (0x8000000000000000UL >> cascade)) {
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unsigned int cirq =
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irq_linear_revmap(iic_host,
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base | cascade);
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if (cirq != NO_IRQ)
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generic_handle_irq(cirq);
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}
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/* post-ack level interrupts */
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ack = bits & ~IIC_ISR_EDGE_MASK;
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if (ack)
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out_be64(&node_iic->iic_is, ack);
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}
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chip->irq_eoi(&desc->irq_data);
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}
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static struct irq_chip iic_ioexc_chip = {
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.name = "CELL-IOEX",
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.irq_mask = iic_mask,
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.irq_unmask = iic_unmask,
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.irq_eoi = iic_ioexc_eoi,
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};
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/* Get an IRQ number from the pending state register of the IIC */
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static unsigned int iic_get_irq(void)
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{
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struct cbe_iic_pending_bits pending;
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struct iic *iic;
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unsigned int virq;
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iic = this_cpu_ptr(&cpu_iic);
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*(unsigned long *) &pending =
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in_be64((u64 __iomem *) &iic->regs->pending_destr);
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if (!(pending.flags & CBE_IIC_IRQ_VALID))
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return NO_IRQ;
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virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
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if (virq == NO_IRQ)
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return NO_IRQ;
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iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
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BUG_ON(iic->eoi_ptr > 15);
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return virq;
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}
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void iic_setup_cpu(void)
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{
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out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
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}
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u8 iic_get_target_id(int cpu)
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{
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return per_cpu(cpu_iic, cpu).target_id;
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}
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EXPORT_SYMBOL_GPL(iic_get_target_id);
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#ifdef CONFIG_SMP
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/* Use the highest interrupt priorities for IPI */
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static inline int iic_msg_to_irq(int msg)
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{
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return IIC_IRQ_TYPE_IPI + 0xf - msg;
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}
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void iic_message_pass(int cpu, int msg)
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{
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out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
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}
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struct irq_domain *iic_get_irq_host(int node)
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{
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return iic_host;
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}
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EXPORT_SYMBOL_GPL(iic_get_irq_host);
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static void iic_request_ipi(int msg)
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{
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int virq;
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virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
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if (virq == NO_IRQ) {
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printk(KERN_ERR
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"iic: failed to map IPI %s\n", smp_ipi_name[msg]);
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return;
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}
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/*
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* If smp_request_message_ipi encounters an error it will notify
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* the error. If a message is not needed it will return non-zero.
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*/
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if (smp_request_message_ipi(virq, msg))
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irq_dispose_mapping(virq);
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}
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void iic_request_IPIs(void)
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{
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iic_request_ipi(PPC_MSG_CALL_FUNCTION);
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iic_request_ipi(PPC_MSG_RESCHEDULE);
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iic_request_ipi(PPC_MSG_TICK_BROADCAST);
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iic_request_ipi(PPC_MSG_DEBUGGER_BREAK);
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}
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#endif /* CONFIG_SMP */
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static int iic_host_match(struct irq_domain *h, struct device_node *node,
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enum irq_domain_bus_token bus_token)
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{
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return of_device_is_compatible(node,
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"IBM,CBEA-Internal-Interrupt-Controller");
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}
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static int iic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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switch (hw & IIC_IRQ_TYPE_MASK) {
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case IIC_IRQ_TYPE_IPI:
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irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
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break;
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case IIC_IRQ_TYPE_IOEXC:
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irq_set_chip_and_handler(virq, &iic_ioexc_chip,
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handle_edge_eoi_irq);
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break;
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default:
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irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
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}
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return 0;
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}
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static int iic_host_xlate(struct irq_domain *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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unsigned int node, ext, unit, class;
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const u32 *val;
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if (!of_device_is_compatible(ct,
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"IBM,CBEA-Internal-Interrupt-Controller"))
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return -ENODEV;
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if (intsize != 1)
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return -ENODEV;
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val = of_get_property(ct, "#interrupt-cells", NULL);
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if (val == NULL || *val != 1)
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return -ENODEV;
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node = intspec[0] >> 24;
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ext = (intspec[0] >> 16) & 0xff;
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class = (intspec[0] >> 8) & 0xff;
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unit = intspec[0] & 0xff;
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/* Check if node is in supported range */
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if (node > 1)
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return -EINVAL;
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/* Build up interrupt number, special case for IO exceptions */
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*out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
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if (unit == IIC_UNIT_IIC && class == 1)
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*out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
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else
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*out_hwirq |= IIC_IRQ_TYPE_NORMAL |
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(class << IIC_IRQ_CLASS_SHIFT) | unit;
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/* Dummy flags, ignored by iic code */
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*out_flags = IRQ_TYPE_EDGE_RISING;
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return 0;
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}
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static const struct irq_domain_ops iic_host_ops = {
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.match = iic_host_match,
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.map = iic_host_map,
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.xlate = iic_host_xlate,
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};
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static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
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struct device_node *node)
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{
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/* XXX FIXME: should locate the linux CPU number from the HW cpu
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* number properly. We are lucky for now
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*/
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struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
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iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
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BUG_ON(iic->regs == NULL);
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iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
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iic->eoi_stack[0] = 0xff;
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iic->node = of_node_get(node);
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out_be64(&iic->regs->prio, 0);
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printk(KERN_INFO "IIC for CPU %d target id 0x%x : %s\n",
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hw_cpu, iic->target_id, node->full_name);
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}
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static int __init setup_iic(void)
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{
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struct device_node *dn;
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struct resource r0, r1;
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unsigned int node, cascade, found = 0;
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struct cbe_iic_regs __iomem *node_iic;
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const u32 *np;
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for (dn = NULL;
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(dn = of_find_node_by_name(dn,"interrupt-controller")) != NULL;) {
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if (!of_device_is_compatible(dn,
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"IBM,CBEA-Internal-Interrupt-Controller"))
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continue;
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np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
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if (np == NULL) {
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printk(KERN_WARNING "IIC: CPU association not found\n");
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of_node_put(dn);
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return -ENODEV;
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}
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if (of_address_to_resource(dn, 0, &r0) ||
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of_address_to_resource(dn, 1, &r1)) {
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printk(KERN_WARNING "IIC: Can't resolve addresses\n");
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of_node_put(dn);
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return -ENODEV;
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}
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found++;
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init_one_iic(np[0], r0.start, dn);
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init_one_iic(np[1], r1.start, dn);
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/* Setup cascade for IO exceptions. XXX cleanup tricks to get
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* node vs CPU etc...
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* Note that we configure the IIC_IRR here with a hard coded
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* priority of 1. We might want to improve that later.
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*/
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node = np[0] >> 1;
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node_iic = cbe_get_cpu_iic_regs(np[0]);
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cascade = node << IIC_IRQ_NODE_SHIFT;
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cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
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cascade |= IIC_UNIT_IIC;
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cascade = irq_create_mapping(iic_host, cascade);
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if (cascade == NO_IRQ)
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continue;
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/*
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* irq_data is a generic pointer that gets passed back
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* to us later, so the forced cast is fine.
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*/
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irq_set_handler_data(cascade, (void __force *)node_iic);
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irq_set_chained_handler(cascade, iic_ioexc_cascade);
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out_be64(&node_iic->iic_ir,
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(1 << 12) /* priority */ |
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(node << 4) /* dest node */ |
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IIC_UNIT_THREAD_0 /* route them to thread 0 */);
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/* Flush pending (make sure it triggers if there is
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* anything pending
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*/
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out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
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}
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if (found)
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return 0;
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else
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return -ENODEV;
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}
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void __init iic_init_IRQ(void)
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{
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/* Setup an irq host data structure */
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iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops,
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NULL);
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BUG_ON(iic_host == NULL);
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irq_set_default_host(iic_host);
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/* Discover and initialize iics */
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if (setup_iic() < 0)
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panic("IIC: Failed to initialize !\n");
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/* Set master interrupt handling function */
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ppc_md.get_irq = iic_get_irq;
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/* Enable on current CPU */
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iic_setup_cpu();
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}
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void iic_set_interrupt_routing(int cpu, int thread, int priority)
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{
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struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
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u64 iic_ir = 0;
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int node = cpu >> 1;
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/* Set which node and thread will handle the next interrupt */
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iic_ir |= CBE_IIC_IR_PRIO(priority) |
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CBE_IIC_IR_DEST_NODE(node);
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if (thread == 0)
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iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
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else
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iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
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out_be64(&iic_regs->iic_ir, iic_ir);
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}
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