92618ff8b0
OMAP2xxx devices have two on-chip APLLs. These APLLs can automatically enter idle when not in use. Connect the APLL autoidle code to the clock code, so that the clock framework can handle this process. As part of this patch, remove the code in mach-omap2/pm24xx.c that previously handled APLL autoidle control. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
156 lines
5 KiB
C
156 lines
5 KiB
C
/*
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* OMAP2/3 Clock Management (CM) register definitions
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*
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* Copyright (C) 2007-2009 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* The CM hardware modules on the OMAP2/3 are quite similar to each
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* other. The CM modules/instances on OMAP4 are quite different, so
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* they are handled in a separate file.
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*/
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#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
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#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H
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#include "prcm-common.h"
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#define OMAP2420_CM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
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#define OMAP2430_CM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
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#define OMAP34XX_CM_REGADDR(module, reg) \
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OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
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/*
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* OMAP3-specific global CM registers
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* Use cm_{read,write}_reg() with these registers.
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* These registers appear once per CM module.
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*/
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#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
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#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
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#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
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#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070
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#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
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/*
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* Module specific CM register offsets from CM_BASE + domain offset
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* Use cm_{read,write}_mod_reg() with these registers.
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* These register offsets generally appear in more than one PRCM submodule.
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*/
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/* Common between OMAP2 and OMAP3 */
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#define CM_FCLKEN 0x0000
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#define CM_FCLKEN1 CM_FCLKEN
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#define CM_CLKEN CM_FCLKEN
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#define CM_ICLKEN 0x0010
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#define CM_ICLKEN1 CM_ICLKEN
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#define CM_ICLKEN2 0x0014
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#define CM_ICLKEN3 0x0018
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#define CM_IDLEST 0x0020
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#define CM_IDLEST1 CM_IDLEST
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#define CM_IDLEST2 0x0024
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#define CM_AUTOIDLE 0x0030
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#define CM_AUTOIDLE1 CM_AUTOIDLE
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#define CM_AUTOIDLE2 0x0034
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#define CM_AUTOIDLE3 0x0038
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#define CM_CLKSEL 0x0040
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#define CM_CLKSEL1 CM_CLKSEL
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#define CM_CLKSEL2 0x0044
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#define OMAP2_CM_CLKSTCTRL 0x0048
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/* OMAP2-specific register offsets */
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#define OMAP24XX_CM_FCLKEN2 0x0004
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#define OMAP24XX_CM_ICLKEN4 0x001c
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#define OMAP24XX_CM_AUTOIDLE4 0x003c
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#define OMAP2430_CM_IDLEST3 0x0028
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/* OMAP3-specific register offsets */
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#define OMAP3430_CM_CLKEN_PLL 0x0004
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#define OMAP3430ES2_CM_CLKEN2 0x0004
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#define OMAP3430ES2_CM_FCLKEN3 0x0008
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#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
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#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
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#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
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#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
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#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
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#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
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#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2
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#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL
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#define OMAP3430_CM_CLKSTST 0x004c
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#define OMAP3430ES2_CM_CLKSEL4 0x004c
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#define OMAP3430ES2_CM_CLKSEL5 0x0050
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#define OMAP3430_CM_CLKSEL2_EMU 0x0050
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#define OMAP3430_CM_CLKSEL3_EMU 0x0054
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/* CM_IDLEST bit field values to indicate deasserted IdleReq */
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#define OMAP24XX_CM_IDLEST_VAL 0
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#define OMAP34XX_CM_IDLEST_VAL 1
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/* Clock management domain register get/set */
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#ifndef __ASSEMBLER__
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extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx);
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extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx);
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extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
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extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id,
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u8 idlest_shift);
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extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx);
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extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx);
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extern bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask);
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extern void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
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extern void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
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extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
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extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
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extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
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extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
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extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
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extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
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extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
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#endif
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/* CM register bits shared between 24XX and 3430 */
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/* CM_CLKSEL_GFX */
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#define OMAP_CLKSEL_GFX_SHIFT 0
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#define OMAP_CLKSEL_GFX_MASK (0x7 << 0)
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/* CM_ICLKEN_GFX */
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#define OMAP_EN_GFX_SHIFT 0
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#define OMAP_EN_GFX_MASK (1 << 0)
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/* CM_IDLEST_GFX */
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#define OMAP_ST_GFX_MASK (1 << 0)
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/* Function prototypes */
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# ifndef __ASSEMBLER__
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extern void omap3_cm_save_context(void);
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extern void omap3_cm_restore_context(void);
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# endif
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#endif
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