26c547fd13
If transceiver is attached to a MMC host of ES2.1 OMAP35xx, it seems 2.1.1.128 erratum doesn't apply and there is no data corruption, probably because of different signal timing. The workaround for this erratum disables multiblock reads, which causes dramatic loss of performance (over 75% slower), so avoid it when transceiver is present. Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> [paul@pwsan.com: edited commit message slightly] Signed-off-by: Paul Walmsley <paul@pwsan.com>
602 lines
15 KiB
C
602 lines
15 KiB
C
/*
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* linux/arch/arm/mach-omap2/hsmmc.c
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*
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* Copyright (C) 2007-2008 Texas Instruments
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* Copyright (C) 2008 Nokia Corporation
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* Author: Texas Instruments
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <plat/mmc.h>
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#include <plat/omap-pm.h>
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#include <plat/mux.h>
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#include <plat/omap_device.h>
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#include "mux.h"
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#include "hsmmc.h"
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#include "control.h"
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#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
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static u16 control_pbias_offset;
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static u16 control_devconf1_offset;
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static u16 control_mmc1;
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#define HSMMC_NAME_LEN 9
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#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
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static int hsmmc_get_context_loss(struct device *dev)
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{
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return omap_pm_get_dev_context_loss_count(dev);
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}
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#else
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#define hsmmc_get_context_loss NULL
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#endif
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static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg, prog_io;
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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if (mmc->slots[0].remux)
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mmc->slots[0].remux(dev, slot, power_on);
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/*
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* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
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* card with Vcc regulator (from twl4030 or whatever). OMAP has both
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* 1.8V and 3.0V modes, controlled by the PBIAS register.
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*
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* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
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* is most naturally TWL VSIM; those pins also use PBIAS.
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*
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* FIXME handle VMMC1A as needed ...
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*/
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if (power_on) {
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if (cpu_is_omap2430()) {
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reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
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if ((1 << vdd) >= MMC_VDD_30_31)
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reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
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else
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reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
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omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
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}
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if (mmc->slots[0].internal_clock) {
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reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
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reg |= OMAP2_MMCSDIO1ADPCLKISEL;
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omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
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}
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reg = omap_ctrl_readl(control_pbias_offset);
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if (cpu_is_omap3630()) {
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/* Set MMC I/O to 52Mhz */
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prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
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prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
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omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
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} else {
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reg |= OMAP2_PBIASSPEEDCTRL0;
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}
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reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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omap_ctrl_writel(reg, control_pbias_offset);
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} else {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg &= ~OMAP2_PBIASLITEPWRDNZ0;
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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}
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static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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/* 100ms delay required for PBIAS configuration */
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msleep(100);
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if (power_on) {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
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if ((1 << vdd) <= MMC_VDD_165_195)
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reg &= ~OMAP2_PBIASLITEVMODE0;
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else
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reg |= OMAP2_PBIASLITEVMODE0;
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omap_ctrl_writel(reg, control_pbias_offset);
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} else {
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reg = omap_ctrl_readl(control_pbias_offset);
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reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
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OMAP2_PBIASLITEVMODE0);
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omap_ctrl_writel(reg, control_pbias_offset);
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}
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}
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static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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/*
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* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
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* card with Vcc regulator (from twl4030 or whatever). OMAP has both
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* 1.8V and 3.0V modes, controlled by the PBIAS register.
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*/
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reg = omap4_ctrl_pad_readl(control_pbias_offset);
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reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
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OMAP4_MMC1_PWRDNZ_MASK |
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OMAP4_MMC1_PBIASLITE_VMODE_MASK);
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omap4_ctrl_pad_writel(reg, control_pbias_offset);
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}
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static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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u32 reg;
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unsigned long timeout;
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if (power_on) {
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reg = omap4_ctrl_pad_readl(control_pbias_offset);
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reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
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if ((1 << vdd) <= MMC_VDD_165_195)
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reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
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else
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reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
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reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
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OMAP4_MMC1_PWRDNZ_MASK);
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omap4_ctrl_pad_writel(reg, control_pbias_offset);
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timeout = jiffies + msecs_to_jiffies(5);
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do {
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reg = omap4_ctrl_pad_readl(control_pbias_offset);
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if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
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break;
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usleep_range(100, 200);
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} while (!time_after(jiffies, timeout));
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if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
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pr_err("Pbias Voltage is not same as LDO\n");
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/* Caution : On VMODE_ERROR Power Down MMC IO */
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reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
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omap4_ctrl_pad_writel(reg, control_pbias_offset);
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}
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}
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}
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static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
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{
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u32 reg;
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reg = omap_ctrl_readl(control_devconf1_offset);
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if (mmc->slots[0].internal_clock)
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reg |= OMAP2_MMCSDIO2ADPCLKISEL;
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else
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reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
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omap_ctrl_writel(reg, control_devconf1_offset);
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}
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static void hsmmc2_before_set_reg(struct device *dev, int slot,
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int power_on, int vdd)
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{
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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if (mmc->slots[0].remux)
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mmc->slots[0].remux(dev, slot, power_on);
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if (power_on)
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hsmmc2_select_input_clk_src(mmc);
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}
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static int am35x_hsmmc2_set_power(struct device *dev, int slot,
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int power_on, int vdd)
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{
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struct omap_mmc_platform_data *mmc = dev->platform_data;
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if (power_on)
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hsmmc2_select_input_clk_src(mmc);
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return 0;
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}
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static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
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int vdd)
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{
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return 0;
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}
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static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
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int controller_nr)
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{
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if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
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(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
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omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
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OMAP_PIN_INPUT_PULLUP);
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if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
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(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
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omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
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OMAP_PIN_INPUT_PULLUP);
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if (cpu_is_omap34xx()) {
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if (controller_nr == 0) {
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omap_mux_init_signal("sdmmc1_clk",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_cmd",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_dat0",
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OMAP_PIN_INPUT_PULLUP);
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if (mmc_controller->slots[0].caps &
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(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
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omap_mux_init_signal("sdmmc1_dat1",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_dat2",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_dat3",
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OMAP_PIN_INPUT_PULLUP);
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}
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if (mmc_controller->slots[0].caps &
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MMC_CAP_8_BIT_DATA) {
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omap_mux_init_signal("sdmmc1_dat4",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_dat5",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_dat6",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc1_dat7",
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OMAP_PIN_INPUT_PULLUP);
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}
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}
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if (controller_nr == 1) {
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/* MMC2 */
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omap_mux_init_signal("sdmmc2_clk",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_cmd",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_dat0",
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OMAP_PIN_INPUT_PULLUP);
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/*
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* For 8 wire configurations, Lines DAT4, 5, 6 and 7
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* need to be muxed in the board-*.c files
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*/
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if (mmc_controller->slots[0].caps &
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(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
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omap_mux_init_signal("sdmmc2_dat1",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_dat2",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_dat3",
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OMAP_PIN_INPUT_PULLUP);
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}
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if (mmc_controller->slots[0].caps &
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MMC_CAP_8_BIT_DATA) {
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omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
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OMAP_PIN_INPUT_PULLUP);
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omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
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OMAP_PIN_INPUT_PULLUP);
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}
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}
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/*
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* For MMC3 the pins need to be muxed in the board-*.c files
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*/
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}
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}
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static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
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struct omap_mmc_platform_data *mmc)
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{
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char *hc_name;
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hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
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if (!hc_name) {
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pr_err("Cannot allocate memory for controller slot name\n");
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kfree(hc_name);
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return -ENOMEM;
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}
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if (c->name)
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strncpy(hc_name, c->name, HSMMC_NAME_LEN);
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else
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snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
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c->mmc, 1);
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mmc->slots[0].name = hc_name;
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mmc->nr_slots = 1;
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mmc->slots[0].caps = c->caps;
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mmc->slots[0].pm_caps = c->pm_caps;
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mmc->slots[0].internal_clock = !c->ext_clock;
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mmc->dma_mask = 0xffffffff;
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mmc->max_freq = c->max_freq;
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if (cpu_is_omap44xx())
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mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
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else
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mmc->reg_offset = 0;
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mmc->get_context_loss_count = hsmmc_get_context_loss;
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mmc->slots[0].switch_pin = c->gpio_cd;
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mmc->slots[0].gpio_wp = c->gpio_wp;
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mmc->slots[0].remux = c->remux;
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mmc->slots[0].init_card = c->init_card;
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if (c->cover_only)
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mmc->slots[0].cover = 1;
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if (c->nonremovable)
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mmc->slots[0].nonremovable = 1;
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if (c->power_saving)
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mmc->slots[0].power_saving = 1;
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if (c->no_off)
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mmc->slots[0].no_off = 1;
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if (c->no_off_init)
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mmc->slots[0].no_regulator_off_init = c->no_off_init;
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if (c->vcc_aux_disable_is_sleep)
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mmc->slots[0].vcc_aux_disable_is_sleep = 1;
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/*
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* NOTE: MMC slots should have a Vcc regulator set up.
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* This may be from a TWL4030-family chip, another
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* controllable regulator, or a fixed supply.
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*
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* temporary HACK: ocr_mask instead of fixed supply
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*/
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if (cpu_is_omap3505() || cpu_is_omap3517())
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mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
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MMC_VDD_26_27 |
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MMC_VDD_27_28 |
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MMC_VDD_29_30 |
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MMC_VDD_30_31 |
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MMC_VDD_31_32;
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else
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mmc->slots[0].ocr_mask = c->ocr_mask;
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if (!cpu_is_omap3517() && !cpu_is_omap3505())
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mmc->slots[0].features |= HSMMC_HAS_PBIAS;
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if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
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mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
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switch (c->mmc) {
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case 1:
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* on-chip level shifting via PBIAS0/PBIAS1 */
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if (cpu_is_omap44xx()) {
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mmc->slots[0].before_set_reg =
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omap4_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap4_hsmmc1_after_set_reg;
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} else {
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mmc->slots[0].before_set_reg =
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omap_hsmmc1_before_set_reg;
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mmc->slots[0].after_set_reg =
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omap_hsmmc1_after_set_reg;
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}
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}
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if (cpu_is_omap3517() || cpu_is_omap3505())
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mmc->slots[0].set_power = nop_mmc_set_power;
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/* OMAP3630 HSMMC1 supports only 4-bit */
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if (cpu_is_omap3630() &&
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(c->caps & MMC_CAP_8_BIT_DATA)) {
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c->caps &= ~MMC_CAP_8_BIT_DATA;
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c->caps |= MMC_CAP_4_BIT_DATA;
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mmc->slots[0].caps = c->caps;
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}
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break;
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case 2:
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if (cpu_is_omap3517() || cpu_is_omap3505())
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mmc->slots[0].set_power = am35x_hsmmc2_set_power;
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if (c->ext_clock)
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c->transceiver = 1;
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if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
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c->caps &= ~MMC_CAP_8_BIT_DATA;
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c->caps |= MMC_CAP_4_BIT_DATA;
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}
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if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
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/* off-chip level shifting, or none */
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mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
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mmc->slots[0].after_set_reg = NULL;
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}
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break;
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case 3:
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case 4:
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case 5:
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mmc->slots[0].before_set_reg = NULL;
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mmc->slots[0].after_set_reg = NULL;
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break;
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default:
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pr_err("MMC%d configuration not supported!\n", c->mmc);
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kfree(hc_name);
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return -ENODEV;
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}
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return 0;
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}
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static int omap_hsmmc_done;
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void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
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{
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struct platform_device *pdev;
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struct omap_mmc_platform_data *mmc_pdata;
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int res;
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if (omap_hsmmc_done != 1)
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return;
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omap_hsmmc_done++;
|
|
|
|
for (; c->mmc; c++) {
|
|
if (!c->deferred)
|
|
continue;
|
|
|
|
pdev = c->pdev;
|
|
if (!pdev)
|
|
continue;
|
|
|
|
mmc_pdata = pdev->dev.platform_data;
|
|
if (!mmc_pdata)
|
|
continue;
|
|
|
|
mmc_pdata->slots[0].switch_pin = c->gpio_cd;
|
|
mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
|
|
|
|
res = omap_device_register(pdev);
|
|
if (res)
|
|
pr_err("Could not late init MMC %s\n",
|
|
c->name);
|
|
}
|
|
}
|
|
|
|
#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
|
|
|
|
static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
|
|
int ctrl_nr)
|
|
{
|
|
struct omap_hwmod *oh;
|
|
struct omap_hwmod *ohs[1];
|
|
struct omap_device *od;
|
|
struct platform_device *pdev;
|
|
char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
|
|
struct omap_mmc_platform_data *mmc_data;
|
|
struct omap_mmc_dev_attr *mmc_dev_attr;
|
|
char *name;
|
|
int res;
|
|
|
|
mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
|
|
if (!mmc_data) {
|
|
pr_err("Cannot allocate memory for mmc device!\n");
|
|
return;
|
|
}
|
|
|
|
res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
|
|
if (res < 0)
|
|
goto free_mmc;
|
|
|
|
omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
|
|
|
|
name = "omap_hsmmc";
|
|
res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
|
|
"mmc%d", ctrl_nr);
|
|
WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
|
|
"String buffer overflow in MMC%d device setup\n", ctrl_nr);
|
|
|
|
oh = omap_hwmod_lookup(oh_name);
|
|
if (!oh) {
|
|
pr_err("Could not look up %s\n", oh_name);
|
|
goto free_name;
|
|
}
|
|
ohs[0] = oh;
|
|
if (oh->dev_attr != NULL) {
|
|
mmc_dev_attr = oh->dev_attr;
|
|
mmc_data->controller_flags = mmc_dev_attr->flags;
|
|
/*
|
|
* erratum 2.1.1.128 doesn't apply if board has
|
|
* a transceiver is attached
|
|
*/
|
|
if (hsmmcinfo->transceiver)
|
|
mmc_data->controller_flags &=
|
|
~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
|
|
}
|
|
|
|
pdev = platform_device_alloc(name, ctrl_nr - 1);
|
|
if (!pdev) {
|
|
pr_err("Could not allocate pdev for %s\n", name);
|
|
goto free_name;
|
|
}
|
|
dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
|
|
|
|
od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
|
|
if (!od) {
|
|
pr_err("Could not allocate od for %s\n", name);
|
|
goto put_pdev;
|
|
}
|
|
|
|
res = platform_device_add_data(pdev, mmc_data,
|
|
sizeof(struct omap_mmc_platform_data));
|
|
if (res) {
|
|
pr_err("Could not add pdata for %s\n", name);
|
|
goto put_pdev;
|
|
}
|
|
|
|
hsmmcinfo->pdev = pdev;
|
|
|
|
if (hsmmcinfo->deferred)
|
|
goto free_mmc;
|
|
|
|
res = omap_device_register(pdev);
|
|
if (res) {
|
|
pr_err("Could not register od for %s\n", name);
|
|
goto free_od;
|
|
}
|
|
|
|
goto free_mmc;
|
|
|
|
free_od:
|
|
omap_device_delete(od);
|
|
|
|
put_pdev:
|
|
platform_device_put(pdev);
|
|
|
|
free_name:
|
|
kfree(mmc_data->slots[0].name);
|
|
|
|
free_mmc:
|
|
kfree(mmc_data);
|
|
}
|
|
|
|
void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
|
|
{
|
|
u32 reg;
|
|
|
|
if (omap_hsmmc_done)
|
|
return;
|
|
|
|
omap_hsmmc_done = 1;
|
|
|
|
if (!cpu_is_omap44xx()) {
|
|
if (cpu_is_omap2430()) {
|
|
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
|
|
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
|
|
} else {
|
|
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
|
|
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
|
|
}
|
|
} else {
|
|
control_pbias_offset =
|
|
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
|
|
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
|
|
reg = omap4_ctrl_pad_readl(control_mmc1);
|
|
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
|
|
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
|
|
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
|
|
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
|
|
reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
|
|
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
|
|
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
|
|
omap4_ctrl_pad_writel(reg, control_mmc1);
|
|
}
|
|
|
|
for (; controllers->mmc; controllers++)
|
|
omap_hsmmc_init_one(controllers, controllers->mmc);
|
|
|
|
}
|
|
|
|
#endif
|