808a8b7377
This adds support for the Allwinner A33 thermal sensor. Unlike the A10, A13 and A31, the Allwinner A33 only has one channel which is dedicated to the thermal sensor. Moreover, its thermal sensor does not generate interruptions, thus we only need to directly read the register storing the temperature value. The MFD used by the A10, A13 and A31, was created to avoid breaking the DT binding, but since the nodes for the ADC weren't there for the A33, it is not needed. Though the A33 does not have an internal ADC, it has a thermal sensor which shares the same registers with GPADC of the already supported SoCs and almost the same bits, for the same purpose (thermal sensor). The thermal sensor behaves exactly the same (except the presence of interrupts or not) on the different SoCs. Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
101 lines
3.6 KiB
C
101 lines
3.6 KiB
C
/* Header of ADC MFD core driver for sunxi platforms
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*
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* Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#ifndef __SUN4I_GPADC__H__
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#define __SUN4I_GPADC__H__
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#define SUN4I_GPADC_CTRL0 0x00
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#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)
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#define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE BIT(23)
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#define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22)
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#define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
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#define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
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#define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
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#define SUN4I_GPADC_CTRL1 0x04
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#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)
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#define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN BIT(9)
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#define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(6)
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#define SUN4I_GPADC_CTRL1_TP_DUAL_EN BIT(5)
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#define SUN4I_GPADC_CTRL1_TP_MODE_EN BIT(4)
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#define SUN4I_GPADC_CTRL1_TP_ADC_SELECT BIT(3)
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#define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))
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#define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(2, 0)
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/* TP_CTRL1 bits for sun6i SOCs */
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#define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(7)
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#define SUN6I_GPADC_CTRL1_TP_DUAL_EN BIT(6)
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#define SUN6I_GPADC_CTRL1_TP_MODE_EN BIT(5)
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#define SUN6I_GPADC_CTRL1_TP_ADC_SELECT BIT(4)
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#define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
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#define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)
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/* TP_CTRL1 bits for sun8i SoCs */
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#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
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#define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7)
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#define SUN4I_GPADC_CTRL2 0x08
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#define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)
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#define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 26)
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#define SUN4I_GPADC_CTRL2_PRE_MEA_EN BIT(24)
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#define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))
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#define SUN4I_GPADC_CTRL3 0x0c
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#define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2)
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#define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
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#define SUN4I_GPADC_TPR 0x18
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#define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16)
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#define SUN4I_GPADC_TPR_TEMP_PERIOD(x) (GENMASK(15, 0) & (x))
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#define SUN4I_GPADC_INT_FIFOC 0x10
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#define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN BIT(18)
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#define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN BIT(17)
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#define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN BIT(16)
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#define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE BIT(13)
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#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0) & (x)) << 8)
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#define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN BIT(7)
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#define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH BIT(4)
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#define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN BIT(1)
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#define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0)
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#define SUN4I_GPADC_INT_FIFOS 0x14
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#define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING BIT(18)
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#define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING BIT(17)
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#define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING BIT(16)
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#define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG BIT(2)
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#define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING BIT(1)
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#define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING BIT(0)
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#define SUN4I_GPADC_CDAT 0x1c
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#define SUN4I_GPADC_TEMP_DATA 0x20
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#define SUN4I_GPADC_DATA 0x24
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#define SUN4I_GPADC_IRQ_FIFO_DATA 0
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#define SUN4I_GPADC_IRQ_TEMP_DATA 1
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/* 10s delay before suspending the IP */
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#define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000
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struct sun4i_gpadc_dev {
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *regmap_irqc;
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void __iomem *base;
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};
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#endif
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