d84083268b
This patch is hdmi display support for exynos drm driver. There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv and some low level code is already in s5p-tv and even headers for register define are almost same. but in this patch, we decide not to consider separated common code with s5p-tv. Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc. 1. mixer. The piece of hardware responsible for mixing and blending multiple data inputs before passing it to an output device. The mixer is capable of handling up to three image layers. One is the output of VP. Other two are images in RGB format. The blending factor, and layers' priority are controlled by mixer's registers. The output is passed to HDMI. 2. vp (video processor). It is used for processing of NV12/NV21 data. An image stored in RAM is accessed by DMA. The output in YCbCr444 format is send to mixer. 3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes pixel data from mixer and transforms it into data frames. The output is send to HDMIPHY interface. 4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to HDMI connector. Basically, it contains a PLL that produces source clock for mixer, vp and hdmi. 5. ddc (display data channel). It is dedicated i2c channel to exchange display information as edid with display monitor. With plane support, exynos hdmi driver fully supports two mixer layes and vp layer. Also vp layer supports multi buffer plane pixel formats having non contigus memory spaces. In exynos drm driver, common drm_hdmi driver to interface with drm framework has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls them. mixer controls all overlay layers in both mixer and vp. Vblank interrupts for hdmi are handled by mixer internally because drm framework cannot support multiple irq id. And pipe number is used to check which display device irq happens. History v2: this version - drm plane feature support to handle overlay layers. - multi buffer plane pixel format support for vp layer. - vp layer support RFCv1: original - at https://lkml.org/lkml/2011/11/4/164 Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
93 lines
2.6 KiB
C
93 lines
2.6 KiB
C
/*
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* Authors:
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* Seung-Woo Kim <sw0312.kim@samsung.com>
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* Inki Dae <inki.dae@samsung.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _EXYNOS_MIXER_H_
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#define _EXYNOS_MIXER_H_
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#define HDMI_OVERLAY_NUMBER 3
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struct hdmi_win_data {
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dma_addr_t dma_addr;
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void __iomem *vaddr;
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dma_addr_t chroma_dma_addr;
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void __iomem *chroma_vaddr;
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uint32_t pixel_format;
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unsigned int bpp;
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unsigned int crtc_x;
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unsigned int crtc_y;
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unsigned int crtc_width;
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unsigned int crtc_height;
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unsigned int fb_x;
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unsigned int fb_y;
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unsigned int fb_width;
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unsigned int fb_height;
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unsigned int mode_width;
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unsigned int mode_height;
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unsigned int scan_flags;
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};
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struct mixer_resources {
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struct device *dev;
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/** interrupt index */
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int irq;
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/** pointer to Mixer registers */
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void __iomem *mixer_regs;
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/** pointer to Video Processor registers */
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void __iomem *vp_regs;
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/** spinlock for protection of registers */
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spinlock_t reg_slock;
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/** other resources */
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struct clk *mixer;
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struct clk *vp;
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struct clk *sclk_mixer;
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struct clk *sclk_hdmi;
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struct clk *sclk_dac;
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};
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struct mixer_context {
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unsigned int default_win;
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struct fb_videomode *default_timing;
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unsigned int default_bpp;
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/** mixer interrupt */
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unsigned int irq;
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/** current crtc pipe for vblank */
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int pipe;
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/** interlace scan mode */
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bool interlace;
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/** vp enabled status */
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bool vp_enabled;
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/** mixer and vp resources */
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struct mixer_resources mixer_res;
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/** overlay window data */
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struct hdmi_win_data win_data[HDMI_OVERLAY_NUMBER];
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};
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#endif
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