![Lars-Peter Clausen](/assets/img/avatar_default.png)
Quite a few drivers have a implementation of the get_timeout_clock callback which simply returns the result of clk_get_rate on the device's clock. This patch adds a common implementation of this to the sdhci-pltfm module and replaces all custom implementations with the common one. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Kevin Liu <kliu5@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
646 lines
17 KiB
C
646 lines
17 KiB
C
/*
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* Freescale eSDHC i.MX controller driver for the platform bus.
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*
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* derived from the OF-version.
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*
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* Copyright (c) 2010 Pengutronix e.K.
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* Author: Wolfram Sang <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/gpio.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/slot-gpio.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_data/mmc-esdhc-imx.h>
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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#define ESDHC_CTRL_D3CD 0x08
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/* VENDOR SPEC register */
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#define ESDHC_VENDOR_SPEC 0xc0
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#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
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#define ESDHC_WTMK_LVL 0x44
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#define ESDHC_MIX_CTRL 0x48
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#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
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/* Bits 3 and 6 are not SDHCI standard definitions */
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#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
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/*
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* Our interpretation of the SDHCI_HOST_CONTROL register
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*/
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#define ESDHC_CTRL_4BITBUS (0x1 << 1)
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#define ESDHC_CTRL_8BITBUS (0x2 << 1)
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#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
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/*
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* There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
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* Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
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* but bit28 is used as the INT DMA ERR in fsl eSDHC design.
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* Define this macro DMA error INT for fsl eSDHC
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*/
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#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
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/*
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* The CMDTYPE of the CMD register (offset 0xE) should be set to
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* "11" when the STOP CMD12 is issued on imx53 to abort one
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* open ended multi-blk IO. Otherwise the TC INT wouldn't
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* be generated.
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* In exact block transfer, the controller doesn't complete the
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* operations automatically as required at the end of the
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* transfer and remains on hold if the abort command is not sent.
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* As a result, the TC flag is not asserted and SW received timeout
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* exeception. Bit1 of Vendor Spec registor is used to fix it.
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*/
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#define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
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enum imx_esdhc_type {
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IMX25_ESDHC,
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IMX35_ESDHC,
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IMX51_ESDHC,
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IMX53_ESDHC,
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IMX6Q_USDHC,
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};
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struct pltfm_imx_data {
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int flags;
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u32 scratchpad;
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enum imx_esdhc_type devtype;
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struct pinctrl *pinctrl;
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struct esdhc_platform_data boarddata;
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struct clk *clk_ipg;
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struct clk *clk_ahb;
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struct clk *clk_per;
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};
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static struct platform_device_id imx_esdhc_devtype[] = {
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{
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.name = "sdhci-esdhc-imx25",
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.driver_data = IMX25_ESDHC,
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}, {
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.name = "sdhci-esdhc-imx35",
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.driver_data = IMX35_ESDHC,
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}, {
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.name = "sdhci-esdhc-imx51",
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.driver_data = IMX51_ESDHC,
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}, {
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.name = "sdhci-esdhc-imx53",
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.driver_data = IMX53_ESDHC,
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}, {
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.name = "sdhci-usdhc-imx6q",
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.driver_data = IMX6Q_USDHC,
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}, {
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/* sentinel */
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}
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};
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MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
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static const struct of_device_id imx_esdhc_dt_ids[] = {
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{ .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
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{ .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
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{ .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
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{ .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
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{ .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
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static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
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{
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return data->devtype == IMX25_ESDHC;
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}
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static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
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{
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return data->devtype == IMX35_ESDHC;
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}
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static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
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{
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return data->devtype == IMX51_ESDHC;
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}
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static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
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{
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return data->devtype == IMX53_ESDHC;
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}
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static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
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{
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return data->devtype == IMX6Q_USDHC;
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}
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static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
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{
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void __iomem *base = host->ioaddr + (reg & ~0x3);
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u32 shift = (reg & 0x3) * 8;
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writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
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}
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static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
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{
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u32 val = readl(host->ioaddr + reg);
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if (unlikely(reg == SDHCI_CAPABILITIES)) {
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/* In FSL esdhc IC module, only bit20 is used to indicate the
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* ADMA2 capability of esdhc, but this bit is messed up on
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* some SOCs (e.g. on MX25, MX35 this bit is set, but they
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* don't actually support ADMA2). So set the BROKEN_ADMA
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* uirk on MX25/35 platforms.
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*/
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if (val & SDHCI_CAN_DO_ADMA1) {
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val &= ~SDHCI_CAN_DO_ADMA1;
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val |= SDHCI_CAN_DO_ADMA2;
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}
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}
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if (unlikely(reg == SDHCI_INT_STATUS)) {
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if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
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val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
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val |= SDHCI_INT_ADMA_ERROR;
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}
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}
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return val;
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}
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static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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u32 data;
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if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
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if (val & SDHCI_INT_CARD_INT) {
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/*
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* Clear and then set D3CD bit to avoid missing the
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* card interrupt. This is a eSDHC controller problem
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* so we need to apply the following workaround: clear
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* and set D3CD bit will make eSDHC re-sample the card
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* interrupt. In case a card interrupt was lost,
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* re-sample it by the following steps.
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*/
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data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
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data &= ~ESDHC_CTRL_D3CD;
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writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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data |= ESDHC_CTRL_D3CD;
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writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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}
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if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
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&& (reg == SDHCI_INT_STATUS)
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&& (val & SDHCI_INT_DATA_END))) {
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u32 v;
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v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
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v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
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writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
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}
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if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
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if (val & SDHCI_INT_ADMA_ERROR) {
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val &= ~SDHCI_INT_ADMA_ERROR;
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val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
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}
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}
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writel(val, host->ioaddr + reg);
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}
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static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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if (unlikely(reg == SDHCI_HOST_VERSION)) {
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reg ^= 2;
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if (is_imx6q_usdhc(imx_data)) {
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/*
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* The usdhc register returns a wrong host version.
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* Correct it here.
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*/
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return SDHCI_SPEC_300;
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}
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}
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return readw(host->ioaddr + reg);
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}
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static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
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&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
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&& (host->cmd->data->blocks > 1)
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&& (host->cmd->data->flags & MMC_DATA_READ)) {
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u32 v;
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v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
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v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
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writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
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}
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if (is_imx6q_usdhc(imx_data)) {
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u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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/* Swap AC23 bit */
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if (val & SDHCI_TRNS_AUTO_CMD23) {
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val &= ~SDHCI_TRNS_AUTO_CMD23;
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val |= ESDHC_MIX_CTRL_AC23EN;
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}
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m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
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writel(m, host->ioaddr + ESDHC_MIX_CTRL);
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} else {
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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imx_data->scratchpad = val;
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}
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return;
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case SDHCI_COMMAND:
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if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
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host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
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(imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
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val |= SDHCI_CMD_ABORTCMD;
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if (is_imx6q_usdhc(imx_data))
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writel(val << 16,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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else
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writel(val << 16 | imx_data->scratchpad,
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host->ioaddr + SDHCI_TRANSFER_MODE);
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return;
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case SDHCI_BLOCK_SIZE:
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val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
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break;
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}
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esdhc_clrset_le(host, 0xffff, val, reg);
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}
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static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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u32 new_val;
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u32 mask;
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switch (reg) {
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case SDHCI_POWER_CONTROL:
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/*
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* FSL put some DMA bits here
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* If your board has a regulator, code should be here
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*/
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return;
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case SDHCI_HOST_CONTROL:
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/* FSL messed up here, so we need to manually compose it. */
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new_val = val & SDHCI_CTRL_LED;
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/* ensure the endianness */
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new_val |= ESDHC_HOST_CONTROL_LE;
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/* bits 8&9 are reserved on mx25 */
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if (!is_imx25_esdhc(imx_data)) {
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/* DMA mode bits are shifted */
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new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
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}
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/*
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* Do not touch buswidth bits here. This is done in
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* esdhc_pltfm_bus_width.
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*/
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mask = 0xffff & ~ESDHC_CTRL_BUSWIDTH_MASK;
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esdhc_clrset_le(host, mask, new_val, reg);
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return;
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}
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esdhc_clrset_le(host, 0xff, val, reg);
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/*
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* The esdhc has a design violation to SDHC spec which tells
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* that software reset should not affect card detection circuit.
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* But esdhc clears its SYSCTL register bits [0..2] during the
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* software reset. This will stop those clocks that card detection
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* circuit relies on. To work around it, we turn the clocks on back
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* to keep card detection circuit functional.
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*/
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if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
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esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
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/*
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* The reset on usdhc fails to clear MIX_CTRL register.
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* Do it manually here.
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*/
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if (is_imx6q_usdhc(imx_data))
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writel(0, host->ioaddr + ESDHC_MIX_CTRL);
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}
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}
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static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return clk_get_rate(pltfm_host->clk) / 256 / 16;
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}
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static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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struct esdhc_platform_data *boarddata = &imx_data->boarddata;
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switch (boarddata->wp_type) {
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case ESDHC_WP_GPIO:
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return mmc_gpio_get_ro(host->mmc);
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case ESDHC_WP_CONTROLLER:
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return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
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SDHCI_WRITE_PROTECT);
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case ESDHC_WP_NONE:
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break;
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}
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return -ENOSYS;
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}
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static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
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{
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u32 ctrl;
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switch (width) {
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case MMC_BUS_WIDTH_8:
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ctrl = ESDHC_CTRL_8BITBUS;
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break;
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case MMC_BUS_WIDTH_4:
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ctrl = ESDHC_CTRL_4BITBUS;
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break;
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default:
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ctrl = 0;
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break;
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}
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esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
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SDHCI_HOST_CONTROL);
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return 0;
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}
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static struct sdhci_ops sdhci_esdhc_ops = {
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.read_l = esdhc_readl_le,
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.read_w = esdhc_readw_le,
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.write_l = esdhc_writel_le,
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.write_w = esdhc_writew_le,
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.write_b = esdhc_writeb_le,
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.set_clock = esdhc_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.get_min_clock = esdhc_pltfm_get_min_clock,
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.get_ro = esdhc_pltfm_get_ro,
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.platform_bus_width = esdhc_pltfm_bus_width,
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};
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static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
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.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
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| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
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| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
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| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
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.ops = &sdhci_esdhc_ops,
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};
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#ifdef CONFIG_OF
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static int
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sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
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struct esdhc_platform_data *boarddata)
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{
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struct device_node *np = pdev->dev.of_node;
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if (!np)
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return -ENODEV;
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if (of_get_property(np, "non-removable", NULL))
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boarddata->cd_type = ESDHC_CD_PERMANENT;
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if (of_get_property(np, "fsl,cd-controller", NULL))
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boarddata->cd_type = ESDHC_CD_CONTROLLER;
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if (of_get_property(np, "fsl,wp-controller", NULL))
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boarddata->wp_type = ESDHC_WP_CONTROLLER;
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boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
|
|
if (gpio_is_valid(boarddata->cd_gpio))
|
|
boarddata->cd_type = ESDHC_CD_GPIO;
|
|
|
|
boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
|
|
if (gpio_is_valid(boarddata->wp_gpio))
|
|
boarddata->wp_type = ESDHC_WP_GPIO;
|
|
|
|
of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static inline int
|
|
sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
|
|
struct esdhc_platform_data *boarddata)
|
|
{
|
|
return -ENODEV;
|
|
}
|
|
#endif
|
|
|
|
static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
|
|
{
|
|
const struct of_device_id *of_id =
|
|
of_match_device(imx_esdhc_dt_ids, &pdev->dev);
|
|
struct sdhci_pltfm_host *pltfm_host;
|
|
struct sdhci_host *host;
|
|
struct esdhc_platform_data *boarddata;
|
|
int err;
|
|
struct pltfm_imx_data *imx_data;
|
|
|
|
host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
|
|
if (IS_ERR(host))
|
|
return PTR_ERR(host);
|
|
|
|
pltfm_host = sdhci_priv(host);
|
|
|
|
imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
|
|
if (!imx_data) {
|
|
err = -ENOMEM;
|
|
goto free_sdhci;
|
|
}
|
|
|
|
if (of_id)
|
|
pdev->id_entry = of_id->data;
|
|
imx_data->devtype = pdev->id_entry->driver_data;
|
|
pltfm_host->priv = imx_data;
|
|
|
|
imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
|
|
if (IS_ERR(imx_data->clk_ipg)) {
|
|
err = PTR_ERR(imx_data->clk_ipg);
|
|
goto free_sdhci;
|
|
}
|
|
|
|
imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
|
|
if (IS_ERR(imx_data->clk_ahb)) {
|
|
err = PTR_ERR(imx_data->clk_ahb);
|
|
goto free_sdhci;
|
|
}
|
|
|
|
imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
|
|
if (IS_ERR(imx_data->clk_per)) {
|
|
err = PTR_ERR(imx_data->clk_per);
|
|
goto free_sdhci;
|
|
}
|
|
|
|
pltfm_host->clk = imx_data->clk_per;
|
|
|
|
clk_prepare_enable(imx_data->clk_per);
|
|
clk_prepare_enable(imx_data->clk_ipg);
|
|
clk_prepare_enable(imx_data->clk_ahb);
|
|
|
|
imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
|
|
if (IS_ERR(imx_data->pinctrl)) {
|
|
err = PTR_ERR(imx_data->pinctrl);
|
|
goto disable_clk;
|
|
}
|
|
|
|
host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
|
|
|
|
if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
|
|
/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
|
|
host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
|
|
| SDHCI_QUIRK_BROKEN_ADMA;
|
|
|
|
if (is_imx53_esdhc(imx_data))
|
|
imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
|
|
|
|
/*
|
|
* The imx6q ROM code will change the default watermark level setting
|
|
* to something insane. Change it back here.
|
|
*/
|
|
if (is_imx6q_usdhc(imx_data))
|
|
writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
|
|
|
|
boarddata = &imx_data->boarddata;
|
|
if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
|
|
if (!host->mmc->parent->platform_data) {
|
|
dev_err(mmc_dev(host->mmc), "no board data!\n");
|
|
err = -EINVAL;
|
|
goto disable_clk;
|
|
}
|
|
imx_data->boarddata = *((struct esdhc_platform_data *)
|
|
host->mmc->parent->platform_data);
|
|
}
|
|
|
|
/* write_protect */
|
|
if (boarddata->wp_type == ESDHC_WP_GPIO) {
|
|
err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
|
|
if (err) {
|
|
dev_err(mmc_dev(host->mmc),
|
|
"failed to request write-protect gpio!\n");
|
|
goto disable_clk;
|
|
}
|
|
host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
|
|
}
|
|
|
|
/* card_detect */
|
|
switch (boarddata->cd_type) {
|
|
case ESDHC_CD_GPIO:
|
|
err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
|
|
if (err) {
|
|
dev_err(mmc_dev(host->mmc),
|
|
"failed to request card-detect gpio!\n");
|
|
goto disable_clk;
|
|
}
|
|
/* fall through */
|
|
|
|
case ESDHC_CD_CONTROLLER:
|
|
/* we have a working card_detect back */
|
|
host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
|
|
break;
|
|
|
|
case ESDHC_CD_PERMANENT:
|
|
host->mmc->caps = MMC_CAP_NONREMOVABLE;
|
|
break;
|
|
|
|
case ESDHC_CD_NONE:
|
|
break;
|
|
}
|
|
|
|
switch (boarddata->max_bus_width) {
|
|
case 8:
|
|
host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
|
|
break;
|
|
case 4:
|
|
host->mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
break;
|
|
case 1:
|
|
default:
|
|
host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
|
|
break;
|
|
}
|
|
|
|
err = sdhci_add_host(host);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(imx_data->clk_per);
|
|
clk_disable_unprepare(imx_data->clk_ipg);
|
|
clk_disable_unprepare(imx_data->clk_ahb);
|
|
free_sdhci:
|
|
sdhci_pltfm_free(pdev);
|
|
return err;
|
|
}
|
|
|
|
static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
|
|
{
|
|
struct sdhci_host *host = platform_get_drvdata(pdev);
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
|
struct pltfm_imx_data *imx_data = pltfm_host->priv;
|
|
int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
|
|
|
|
sdhci_remove_host(host, dead);
|
|
|
|
clk_disable_unprepare(imx_data->clk_per);
|
|
clk_disable_unprepare(imx_data->clk_ipg);
|
|
clk_disable_unprepare(imx_data->clk_ahb);
|
|
|
|
sdhci_pltfm_free(pdev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver sdhci_esdhc_imx_driver = {
|
|
.driver = {
|
|
.name = "sdhci-esdhc-imx",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = imx_esdhc_dt_ids,
|
|
.pm = SDHCI_PLTFM_PMOPS,
|
|
},
|
|
.id_table = imx_esdhc_devtype,
|
|
.probe = sdhci_esdhc_imx_probe,
|
|
.remove = sdhci_esdhc_imx_remove,
|
|
};
|
|
|
|
module_platform_driver(sdhci_esdhc_imx_driver);
|
|
|
|
MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
|
|
MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
|
|
MODULE_LICENSE("GPL v2");
|