![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
866 lines
21 KiB
C
866 lines
21 KiB
C
/* iommu.c: Generic sparc64 IOMMU support.
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*
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* Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/iommu-helper.h>
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#include <linux/bitmap.h>
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#ifdef CONFIG_PCI
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#include <linux/pci.h>
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#endif
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#include <asm/iommu.h>
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#include "iommu_common.h"
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#define STC_CTXMATCH_ADDR(STC, CTX) \
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((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
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#define STC_FLUSHFLAG_INIT(STC) \
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(*((STC)->strbuf_flushflag) = 0UL)
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#define STC_FLUSHFLAG_SET(STC) \
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(*((STC)->strbuf_flushflag) != 0UL)
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#define iommu_read(__reg) \
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({ u64 __ret; \
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__asm__ __volatile__("ldxa [%1] %2, %0" \
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: "=r" (__ret) \
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: "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
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: "memory"); \
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__ret; \
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})
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#define iommu_write(__reg, __val) \
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__asm__ __volatile__("stxa %0, [%1] %2" \
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: /* no outputs */ \
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: "r" (__val), "r" (__reg), \
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"i" (ASI_PHYS_BYPASS_EC_E))
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/* Must be invoked under the IOMMU lock. */
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static void iommu_flushall(struct iommu *iommu)
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{
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if (iommu->iommu_flushinv) {
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iommu_write(iommu->iommu_flushinv, ~(u64)0);
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} else {
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unsigned long tag;
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int entry;
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tag = iommu->iommu_tags;
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for (entry = 0; entry < 16; entry++) {
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iommu_write(tag, 0);
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tag += 8;
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}
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/* Ensure completion of previous PIO writes. */
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(void) iommu_read(iommu->write_complete_reg);
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}
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}
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#define IOPTE_CONSISTENT(CTX) \
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(IOPTE_VALID | IOPTE_CACHE | \
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(((CTX) << 47) & IOPTE_CONTEXT))
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#define IOPTE_STREAMING(CTX) \
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(IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
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/* Existing mappings are never marked invalid, instead they
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* are pointed to a dummy page.
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*/
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#define IOPTE_IS_DUMMY(iommu, iopte) \
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((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
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static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
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{
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unsigned long val = iopte_val(*iopte);
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val &= ~IOPTE_PAGE;
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val |= iommu->dummy_page_pa;
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iopte_val(*iopte) = val;
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}
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/* Based almost entirely upon the ppc64 iommu allocator. If you use the 'handle'
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* facility it must all be done in one pass while under the iommu lock.
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*
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* On sun4u platforms, we only flush the IOMMU once every time we've passed
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* over the entire page table doing allocations. Therefore we only ever advance
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* the hint and cannot backtrack it.
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*/
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unsigned long iommu_range_alloc(struct device *dev,
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struct iommu *iommu,
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unsigned long npages,
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unsigned long *handle)
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{
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unsigned long n, end, start, limit, boundary_size;
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struct iommu_arena *arena = &iommu->arena;
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int pass = 0;
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/* This allocator was derived from x86_64's bit string search */
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/* Sanity check */
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if (unlikely(npages == 0)) {
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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}
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if (handle && *handle)
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start = *handle;
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else
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start = arena->hint;
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limit = arena->limit;
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/* The case below can happen if we have a small segment appended
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* to a large, or when the previous alloc was at the very end of
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* the available space. If so, go back to the beginning and flush.
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*/
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if (start >= limit) {
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start = 0;
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if (iommu->flush_all)
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iommu->flush_all(iommu);
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}
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again:
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if (dev)
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boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
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1 << IO_PAGE_SHIFT);
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else
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boundary_size = ALIGN(1UL << 32, 1 << IO_PAGE_SHIFT);
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n = iommu_area_alloc(arena->map, limit, start, npages,
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iommu->page_table_map_base >> IO_PAGE_SHIFT,
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boundary_size >> IO_PAGE_SHIFT, 0);
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if (n == -1) {
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if (likely(pass < 1)) {
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/* First failure, rescan from the beginning. */
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start = 0;
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if (iommu->flush_all)
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iommu->flush_all(iommu);
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pass++;
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goto again;
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} else {
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/* Second failure, give up */
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return DMA_ERROR_CODE;
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}
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}
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end = n + npages;
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arena->hint = end;
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/* Update handle for SG allocations */
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if (handle)
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*handle = end;
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return n;
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}
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void iommu_range_free(struct iommu *iommu, dma_addr_t dma_addr, unsigned long npages)
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{
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struct iommu_arena *arena = &iommu->arena;
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unsigned long entry;
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entry = (dma_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
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bitmap_clear(arena->map, entry, npages);
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}
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int iommu_table_init(struct iommu *iommu, int tsbsize,
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u32 dma_offset, u32 dma_addr_mask,
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int numa_node)
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{
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unsigned long i, order, sz, num_tsb_entries;
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struct page *page;
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num_tsb_entries = tsbsize / sizeof(iopte_t);
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/* Setup initial software IOMMU state. */
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spin_lock_init(&iommu->lock);
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iommu->ctx_lowest_free = 1;
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iommu->page_table_map_base = dma_offset;
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iommu->dma_addr_mask = dma_addr_mask;
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/* Allocate and initialize the free area map. */
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sz = num_tsb_entries / 8;
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sz = (sz + 7UL) & ~7UL;
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iommu->arena.map = kmalloc_node(sz, GFP_KERNEL, numa_node);
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if (!iommu->arena.map) {
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printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
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return -ENOMEM;
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}
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memset(iommu->arena.map, 0, sz);
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iommu->arena.limit = num_tsb_entries;
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if (tlb_type != hypervisor)
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iommu->flush_all = iommu_flushall;
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/* Allocate and initialize the dummy page which we
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* set inactive IO PTEs to point to.
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*/
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page = alloc_pages_node(numa_node, GFP_KERNEL, 0);
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if (!page) {
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printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
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goto out_free_map;
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}
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iommu->dummy_page = (unsigned long) page_address(page);
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memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
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iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
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/* Now allocate and setup the IOMMU page table itself. */
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order = get_order(tsbsize);
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page = alloc_pages_node(numa_node, GFP_KERNEL, order);
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if (!page) {
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printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
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goto out_free_dummy_page;
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}
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iommu->page_table = (iopte_t *)page_address(page);
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for (i = 0; i < num_tsb_entries; i++)
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iopte_make_dummy(iommu, &iommu->page_table[i]);
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return 0;
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out_free_dummy_page:
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free_page(iommu->dummy_page);
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iommu->dummy_page = 0UL;
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out_free_map:
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kfree(iommu->arena.map);
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iommu->arena.map = NULL;
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return -ENOMEM;
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}
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static inline iopte_t *alloc_npages(struct device *dev, struct iommu *iommu,
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unsigned long npages)
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{
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unsigned long entry;
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entry = iommu_range_alloc(dev, iommu, npages, NULL);
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if (unlikely(entry == DMA_ERROR_CODE))
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return NULL;
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return iommu->page_table + entry;
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}
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static int iommu_alloc_ctx(struct iommu *iommu)
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{
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int lowest = iommu->ctx_lowest_free;
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int sz = IOMMU_NUM_CTXS - lowest;
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int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
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if (unlikely(n == sz)) {
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n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
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if (unlikely(n == lowest)) {
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printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
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n = 0;
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}
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}
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if (n)
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__set_bit(n, iommu->ctx_bitmap);
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return n;
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}
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static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
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{
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if (likely(ctx)) {
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__clear_bit(ctx, iommu->ctx_bitmap);
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if (ctx < iommu->ctx_lowest_free)
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iommu->ctx_lowest_free = ctx;
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}
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}
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static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t *dma_addrp, gfp_t gfp)
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{
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unsigned long flags, order, first_page;
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struct iommu *iommu;
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struct page *page;
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int npages, nid;
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iopte_t *iopte;
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void *ret;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (order >= 10)
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return NULL;
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nid = dev->archdata.numa_node;
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page = alloc_pages_node(nid, gfp, order);
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if (unlikely(!page))
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return NULL;
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first_page = (unsigned long) page_address(page);
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = dev->archdata.iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(iopte == NULL)) {
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free_pages(first_page, order);
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return NULL;
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}
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*dma_addrp = (iommu->page_table_map_base +
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((iopte - iommu->page_table) << IO_PAGE_SHIFT));
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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first_page = __pa(first_page);
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while (npages--) {
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iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
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IOPTE_WRITE |
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(first_page & IOPTE_PAGE));
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iopte++;
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first_page += IO_PAGE_SIZE;
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}
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return ret;
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}
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static void dma_4u_free_coherent(struct device *dev, size_t size,
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void *cpu, dma_addr_t dvma)
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{
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struct iommu *iommu;
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iopte_t *iopte;
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unsigned long flags, order, npages;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = dev->archdata.iommu;
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iopte = iommu->page_table +
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((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
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spin_lock_irqsave(&iommu->lock, flags);
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iommu_range_free(iommu, dvma, npages);
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spin_unlock_irqrestore(&iommu->lock, flags);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t sz,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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struct iommu *iommu;
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struct strbuf *strbuf;
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iopte_t *base;
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unsigned long flags, npages, oaddr;
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unsigned long i, base_paddr, ctx;
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u32 bus_addr, ret;
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unsigned long iopte_protection;
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iommu = dev->archdata.iommu;
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strbuf = dev->archdata.stc;
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if (unlikely(direction == DMA_NONE))
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goto bad_no_ctx;
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oaddr = (unsigned long)(page_address(page) + offset);
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npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
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npages >>= IO_PAGE_SHIFT;
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spin_lock_irqsave(&iommu->lock, flags);
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base = alloc_npages(dev, iommu, npages);
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ctx = 0;
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if (iommu->iommu_ctxflush)
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ctx = iommu_alloc_ctx(iommu);
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spin_unlock_irqrestore(&iommu->lock, flags);
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if (unlikely(!base))
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goto bad;
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bus_addr = (iommu->page_table_map_base +
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((base - iommu->page_table) << IO_PAGE_SHIFT));
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ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
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base_paddr = __pa(oaddr & IO_PAGE_MASK);
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if (strbuf->strbuf_enabled)
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iopte_protection = IOPTE_STREAMING(ctx);
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else
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iopte_protection = IOPTE_CONSISTENT(ctx);
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if (direction != DMA_TO_DEVICE)
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iopte_protection |= IOPTE_WRITE;
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for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
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iopte_val(*base) = iopte_protection | base_paddr;
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return ret;
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bad:
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iommu_free_ctx(iommu, ctx);
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bad_no_ctx:
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if (printk_ratelimit())
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WARN_ON(1);
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return DMA_ERROR_CODE;
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}
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static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
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u32 vaddr, unsigned long ctx, unsigned long npages,
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enum dma_data_direction direction)
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{
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int limit;
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if (strbuf->strbuf_ctxflush &&
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iommu->iommu_ctxflush) {
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unsigned long matchreg, flushreg;
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u64 val;
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flushreg = strbuf->strbuf_ctxflush;
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matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
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iommu_write(flushreg, ctx);
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val = iommu_read(matchreg);
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val &= 0xffff;
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if (!val)
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goto do_flush_sync;
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while (val) {
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if (val & 0x1)
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iommu_write(flushreg, ctx);
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val >>= 1;
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}
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val = iommu_read(matchreg);
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if (unlikely(val)) {
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printk(KERN_WARNING "strbuf_flush: ctx flush "
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"timeout matchreg[%llx] ctx[%lx]\n",
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val, ctx);
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goto do_page_flush;
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}
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} else {
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unsigned long i;
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do_page_flush:
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for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
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iommu_write(strbuf->strbuf_pflush, vaddr);
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}
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|
do_flush_sync:
|
|
/* If the device could not have possibly put dirty data into
|
|
* the streaming cache, no flush-flag synchronization needs
|
|
* to be performed.
|
|
*/
|
|
if (direction == DMA_TO_DEVICE)
|
|
return;
|
|
|
|
STC_FLUSHFLAG_INIT(strbuf);
|
|
iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
|
|
(void) iommu_read(iommu->write_complete_reg);
|
|
|
|
limit = 100000;
|
|
while (!STC_FLUSHFLAG_SET(strbuf)) {
|
|
limit--;
|
|
if (!limit)
|
|
break;
|
|
udelay(1);
|
|
rmb();
|
|
}
|
|
if (!limit)
|
|
printk(KERN_WARNING "strbuf_flush: flushflag timeout "
|
|
"vaddr[%08x] ctx[%lx] npages[%ld]\n",
|
|
vaddr, ctx, npages);
|
|
}
|
|
|
|
static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
|
|
size_t sz, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
iopte_t *base;
|
|
unsigned long flags, npages, ctx, i;
|
|
|
|
if (unlikely(direction == DMA_NONE)) {
|
|
if (printk_ratelimit())
|
|
WARN_ON(1);
|
|
return;
|
|
}
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
npages >>= IO_PAGE_SHIFT;
|
|
base = iommu->page_table +
|
|
((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
/* Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush)
|
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
|
|
|
/* Step 1: Kick data out of streaming buffers if necessary. */
|
|
if (strbuf->strbuf_enabled)
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx,
|
|
npages, direction);
|
|
|
|
/* Step 2: Clear out TSB entries. */
|
|
for (i = 0; i < npages; i++)
|
|
iopte_make_dummy(iommu, base + i);
|
|
|
|
iommu_range_free(iommu, bus_addr, npages);
|
|
|
|
iommu_free_ctx(iommu, ctx);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
struct scatterlist *s, *outs, *segstart;
|
|
unsigned long flags, handle, prot, ctx;
|
|
dma_addr_t dma_next = 0, dma_addr;
|
|
unsigned int max_seg_size;
|
|
unsigned long seg_boundary_size;
|
|
int outcount, incount, i;
|
|
struct strbuf *strbuf;
|
|
struct iommu *iommu;
|
|
unsigned long base_shift;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
if (nelems == 0 || !iommu)
|
|
return 0;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush)
|
|
ctx = iommu_alloc_ctx(iommu);
|
|
|
|
if (strbuf->strbuf_enabled)
|
|
prot = IOPTE_STREAMING(ctx);
|
|
else
|
|
prot = IOPTE_CONSISTENT(ctx);
|
|
if (direction != DMA_TO_DEVICE)
|
|
prot |= IOPTE_WRITE;
|
|
|
|
outs = s = segstart = &sglist[0];
|
|
outcount = 1;
|
|
incount = nelems;
|
|
handle = 0;
|
|
|
|
/* Init first segment length for backout at failure */
|
|
outs->dma_length = 0;
|
|
|
|
max_seg_size = dma_get_max_seg_size(dev);
|
|
seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
|
|
IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
|
|
base_shift = iommu->page_table_map_base >> IO_PAGE_SHIFT;
|
|
for_each_sg(sglist, s, nelems, i) {
|
|
unsigned long paddr, npages, entry, out_entry = 0, slen;
|
|
iopte_t *base;
|
|
|
|
slen = s->length;
|
|
/* Sanity check */
|
|
if (slen == 0) {
|
|
dma_next = 0;
|
|
continue;
|
|
}
|
|
/* Allocate iommu entries for that segment */
|
|
paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
|
|
npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
|
|
entry = iommu_range_alloc(dev, iommu, npages, &handle);
|
|
|
|
/* Handle failure */
|
|
if (unlikely(entry == DMA_ERROR_CODE)) {
|
|
if (printk_ratelimit())
|
|
printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
|
|
" npages %lx\n", iommu, paddr, npages);
|
|
goto iommu_map_failed;
|
|
}
|
|
|
|
base = iommu->page_table + entry;
|
|
|
|
/* Convert entry to a dma_addr_t */
|
|
dma_addr = iommu->page_table_map_base +
|
|
(entry << IO_PAGE_SHIFT);
|
|
dma_addr |= (s->offset & ~IO_PAGE_MASK);
|
|
|
|
/* Insert into HW table */
|
|
paddr &= IO_PAGE_MASK;
|
|
while (npages--) {
|
|
iopte_val(*base) = prot | paddr;
|
|
base++;
|
|
paddr += IO_PAGE_SIZE;
|
|
}
|
|
|
|
/* If we are in an open segment, try merging */
|
|
if (segstart != s) {
|
|
/* We cannot merge if:
|
|
* - allocated dma_addr isn't contiguous to previous allocation
|
|
*/
|
|
if ((dma_addr != dma_next) ||
|
|
(outs->dma_length + s->length > max_seg_size) ||
|
|
(is_span_boundary(out_entry, base_shift,
|
|
seg_boundary_size, outs, s))) {
|
|
/* Can't merge: create a new segment */
|
|
segstart = s;
|
|
outcount++;
|
|
outs = sg_next(outs);
|
|
} else {
|
|
outs->dma_length += s->length;
|
|
}
|
|
}
|
|
|
|
if (segstart == s) {
|
|
/* This is a new segment, fill entries */
|
|
outs->dma_address = dma_addr;
|
|
outs->dma_length = slen;
|
|
out_entry = entry;
|
|
}
|
|
|
|
/* Calculate next page pointer for contiguous check */
|
|
dma_next = dma_addr + slen;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
if (outcount < incount) {
|
|
outs = sg_next(outs);
|
|
outs->dma_address = DMA_ERROR_CODE;
|
|
outs->dma_length = 0;
|
|
}
|
|
|
|
return outcount;
|
|
|
|
iommu_map_failed:
|
|
for_each_sg(sglist, s, nelems, i) {
|
|
if (s->dma_length != 0) {
|
|
unsigned long vaddr, npages, entry, j;
|
|
iopte_t *base;
|
|
|
|
vaddr = s->dma_address & IO_PAGE_MASK;
|
|
npages = iommu_num_pages(s->dma_address, s->dma_length,
|
|
IO_PAGE_SIZE);
|
|
iommu_range_free(iommu, vaddr, npages);
|
|
|
|
entry = (vaddr - iommu->page_table_map_base)
|
|
>> IO_PAGE_SHIFT;
|
|
base = iommu->page_table + entry;
|
|
|
|
for (j = 0; j < npages; j++)
|
|
iopte_make_dummy(iommu, base + j);
|
|
|
|
s->dma_address = DMA_ERROR_CODE;
|
|
s->dma_length = 0;
|
|
}
|
|
if (s == outs)
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* If contexts are being used, they are the same in all of the mappings
|
|
* we make for a particular SG.
|
|
*/
|
|
static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
|
|
{
|
|
unsigned long ctx = 0;
|
|
|
|
if (iommu->iommu_ctxflush) {
|
|
iopte_t *base;
|
|
u32 bus_addr;
|
|
|
|
bus_addr = sg->dma_address & IO_PAGE_MASK;
|
|
base = iommu->page_table +
|
|
((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
|
|
ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
return ctx;
|
|
}
|
|
|
|
static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
|
|
int nelems, enum dma_data_direction direction,
|
|
struct dma_attrs *attrs)
|
|
{
|
|
unsigned long flags, ctx;
|
|
struct scatterlist *sg;
|
|
struct strbuf *strbuf;
|
|
struct iommu *iommu;
|
|
|
|
BUG_ON(direction == DMA_NONE);
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
ctx = fetch_sg_ctx(iommu, sglist);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
sg = sglist;
|
|
while (nelems--) {
|
|
dma_addr_t dma_handle = sg->dma_address;
|
|
unsigned int len = sg->dma_length;
|
|
unsigned long npages, entry;
|
|
iopte_t *base;
|
|
int i;
|
|
|
|
if (!len)
|
|
break;
|
|
npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
|
|
iommu_range_free(iommu, dma_handle, npages);
|
|
|
|
entry = ((dma_handle - iommu->page_table_map_base)
|
|
>> IO_PAGE_SHIFT);
|
|
base = iommu->page_table + entry;
|
|
|
|
dma_handle &= IO_PAGE_MASK;
|
|
if (strbuf->strbuf_enabled)
|
|
strbuf_flush(strbuf, iommu, dma_handle, ctx,
|
|
npages, direction);
|
|
|
|
for (i = 0; i < npages; i++)
|
|
iopte_make_dummy(iommu, base + i);
|
|
|
|
sg = sg_next(sg);
|
|
}
|
|
|
|
iommu_free_ctx(iommu, ctx);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4u_sync_single_for_cpu(struct device *dev,
|
|
dma_addr_t bus_addr, size_t sz,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
unsigned long flags, ctx, npages;
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
return;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
|
|
npages >>= IO_PAGE_SHIFT;
|
|
bus_addr &= IO_PAGE_MASK;
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush &&
|
|
strbuf->strbuf_ctxflush) {
|
|
iopte_t *iopte;
|
|
|
|
iopte = iommu->page_table +
|
|
((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static void dma_4u_sync_sg_for_cpu(struct device *dev,
|
|
struct scatterlist *sglist, int nelems,
|
|
enum dma_data_direction direction)
|
|
{
|
|
struct iommu *iommu;
|
|
struct strbuf *strbuf;
|
|
unsigned long flags, ctx, npages, i;
|
|
struct scatterlist *sg, *sgprv;
|
|
u32 bus_addr;
|
|
|
|
iommu = dev->archdata.iommu;
|
|
strbuf = dev->archdata.stc;
|
|
|
|
if (!strbuf->strbuf_enabled)
|
|
return;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
|
|
/* Step 1: Record the context, if any. */
|
|
ctx = 0;
|
|
if (iommu->iommu_ctxflush &&
|
|
strbuf->strbuf_ctxflush) {
|
|
iopte_t *iopte;
|
|
|
|
iopte = iommu->page_table +
|
|
((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
|
|
ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
|
|
}
|
|
|
|
/* Step 2: Kick data out of streaming buffers. */
|
|
bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
|
|
sgprv = NULL;
|
|
for_each_sg(sglist, sg, nelems, i) {
|
|
if (sg->dma_length == 0)
|
|
break;
|
|
sgprv = sg;
|
|
}
|
|
|
|
npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
|
|
- bus_addr) >> IO_PAGE_SHIFT;
|
|
strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
|
|
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
static struct dma_map_ops sun4u_dma_ops = {
|
|
.alloc_coherent = dma_4u_alloc_coherent,
|
|
.free_coherent = dma_4u_free_coherent,
|
|
.map_page = dma_4u_map_page,
|
|
.unmap_page = dma_4u_unmap_page,
|
|
.map_sg = dma_4u_map_sg,
|
|
.unmap_sg = dma_4u_unmap_sg,
|
|
.sync_single_for_cpu = dma_4u_sync_single_for_cpu,
|
|
.sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
|
|
};
|
|
|
|
struct dma_map_ops *dma_ops = &sun4u_dma_ops;
|
|
EXPORT_SYMBOL(dma_ops);
|
|
|
|
extern int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask);
|
|
|
|
int dma_supported(struct device *dev, u64 device_mask)
|
|
{
|
|
struct iommu *iommu = dev->archdata.iommu;
|
|
u64 dma_addr_mask = iommu->dma_addr_mask;
|
|
|
|
if (device_mask >= (1UL << 32UL))
|
|
return 0;
|
|
|
|
if ((device_mask & dma_addr_mask) == dma_addr_mask)
|
|
return 1;
|
|
|
|
#ifdef CONFIG_PCI
|
|
if (dev->bus == &pci_bus_type)
|
|
return pci64_dma_supported(to_pci_dev(dev), device_mask);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(dma_supported);
|