![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
226 lines
5.8 KiB
C
226 lines
5.8 KiB
C
/* sun4c_irq.c
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* arch/sparc/kernel/sun4c_irq.c:
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*
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* djhr: Hacked out of irq.c into a CPU dependent version.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
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* Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
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*/
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "irq.h"
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/psr.h>
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#include <asm/vaddrs.h>
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#include <asm/timer.h>
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#include <asm/openprom.h>
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#include <asm/oplib.h>
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#include <asm/traps.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/idprom.h>
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#include <asm/machines.h>
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/* Pointer to the interrupt enable byte
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*
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* Dave Redman (djhr@tadpole.co.uk)
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* What you may not be aware of is that entry.S requires this variable.
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*
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* --- linux_trap_nmi_sun4c --
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*
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* so don't go making it static, like I tried. sigh.
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*/
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unsigned char __iomem *interrupt_enable = NULL;
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static void sun4c_disable_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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unsigned char current_mask, new_mask;
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local_irq_save(flags);
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irq_nr &= (NR_IRQS - 1);
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current_mask = sbus_readb(interrupt_enable);
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switch(irq_nr) {
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case 1:
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new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
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break;
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case 8:
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new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
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break;
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case 10:
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new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
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break;
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case 14:
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new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
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break;
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default:
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local_irq_restore(flags);
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return;
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}
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sbus_writeb(new_mask, interrupt_enable);
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local_irq_restore(flags);
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}
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static void sun4c_enable_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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unsigned char current_mask, new_mask;
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local_irq_save(flags);
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irq_nr &= (NR_IRQS - 1);
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current_mask = sbus_readb(interrupt_enable);
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switch(irq_nr) {
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case 1:
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new_mask = ((current_mask) | SUN4C_INT_E1);
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break;
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case 8:
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new_mask = ((current_mask) | SUN4C_INT_E8);
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break;
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case 10:
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new_mask = ((current_mask) | SUN4C_INT_E10);
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break;
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case 14:
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new_mask = ((current_mask) | SUN4C_INT_E14);
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break;
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default:
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local_irq_restore(flags);
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return;
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}
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sbus_writeb(new_mask, interrupt_enable);
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local_irq_restore(flags);
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}
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struct sun4c_timer_info {
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u32 l10_count;
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u32 l10_limit;
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u32 l14_count;
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u32 l14_limit;
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};
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static struct sun4c_timer_info __iomem *sun4c_timers;
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static void sun4c_clear_clock_irq(void)
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{
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sbus_readl(&sun4c_timers->l10_limit);
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}
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static void sun4c_load_profile_irq(int cpu, unsigned int limit)
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{
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/* Errm.. not sure how to do this.. */
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}
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static void __init sun4c_init_timers(irq_handler_t counter_fn)
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{
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const struct linux_prom_irqs *irq;
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struct device_node *dp;
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const u32 *addr;
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int err;
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dp = of_find_node_by_name(NULL, "counter-timer");
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if (!dp) {
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prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
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prom_halt();
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}
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addr = of_get_property(dp, "address", NULL);
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if (!addr) {
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prom_printf("sun4c_init_timers: No address property\n");
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prom_halt();
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}
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sun4c_timers = (void __iomem *) (unsigned long) addr[0];
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irq = of_get_property(dp, "intr", NULL);
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of_node_put(dp);
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if (!irq) {
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prom_printf("sun4c_init_timers: No intr property\n");
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prom_halt();
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}
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/* Have the level 10 timer tick at 100HZ. We don't touch the
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* level 14 timer limit since we are letting the prom handle
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* them until we have a real console driver so L1-A works.
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*/
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sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
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master_l10_counter = &sun4c_timers->l10_count;
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err = request_irq(irq[0].pri, counter_fn,
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(IRQF_DISABLED | SA_STATIC_ALLOC),
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"timer", NULL);
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if (err) {
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prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
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prom_halt();
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}
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sun4c_disable_irq(irq[1].pri);
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}
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#ifdef CONFIG_SMP
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static void sun4c_nop(void) {}
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#endif
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void __init sun4c_init_IRQ(void)
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{
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struct device_node *dp;
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const u32 *addr;
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dp = of_find_node_by_name(NULL, "interrupt-enable");
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if (!dp) {
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prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
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prom_halt();
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}
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addr = of_get_property(dp, "address", NULL);
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of_node_put(dp);
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if (!addr) {
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prom_printf("sun4c_init_IRQ: No address property\n");
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prom_halt();
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}
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interrupt_enable = (void __iomem *) (unsigned long) addr[0];
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BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
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BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
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sparc_init_timers = sun4c_init_timers;
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#ifdef CONFIG_SMP
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BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
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BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
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#endif
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sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
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/* Cannot enable interrupts until OBP ticker is disabled. */
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}
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