b24212fbfb
The UART controller used in the Armada 370 and Armada XP SoCs is the Synopsys DesignWare 8250 (aka Synopsys DesignWare ABP UART). The improper use of the ns16550 can lead to a kernel oops during boot if a character is sent to the UART before the initialization of the driver. The DW APB has an extra interrupt that gets raised when writing to the LCR when busy. This explains why we need to use dw-apb-uart driver to handle this. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
137 lines
3 KiB
Plaintext
137 lines
3 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions that are common to the Armada
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* 370 and Armada XP SoC.
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*/
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/include/ "skeleton.dtsi"
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/ {
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model = "Marvell Armada 370 and XP SoC";
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compatible = "marvell,armada-370-xp";
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cpus {
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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};
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};
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mpic: interrupt-controller@d0020000 {
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compatible = "marvell,mpic";
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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};
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coherency-fabric@d0020200 {
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compatible = "marvell,coherency-fabric";
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reg = <0xd0020200 0xb0>,
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<0xd0021810 0x1c>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&mpic>;
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ranges;
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serial@d0012000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012000 0x100>;
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reg-shift = <2>;
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interrupts = <41>;
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reg-io-width = <4>;
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status = "disabled";
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};
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serial@d0012100 {
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compatible = "snps,dw-apb-uart";
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reg = <0xd0012100 0x100>;
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reg-shift = <2>;
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interrupts = <42>;
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reg-io-width = <4>;
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status = "disabled";
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};
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timer@d0020300 {
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compatible = "marvell,armada-370-xp-timer";
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reg = <0xd0020300 0x30>;
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interrupts = <37>, <38>, <39>, <40>;
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clocks = <&coreclk 2>;
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};
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addr-decoding@d0020000 {
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compatible = "marvell,armada-addr-decoding-controller";
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reg = <0xd0020000 0x258>;
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};
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sata@d00a0000 {
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compatible = "marvell,orion-sata";
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reg = <0xd00a0000 0x2400>;
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interrupts = <55>;
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clocks = <&gateclk 15>, <&gateclk 30>;
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clock-names = "0", "1";
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status = "disabled";
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0xd0072004 0x4>;
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};
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ethernet@d0070000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0070000 0x2500>;
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interrupts = <8>;
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clocks = <&gateclk 4>;
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status = "disabled";
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};
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ethernet@d0074000 {
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compatible = "marvell,armada-370-neta";
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reg = <0xd0074000 0x2500>;
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interrupts = <10>;
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clocks = <&gateclk 3>;
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status = "disabled";
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};
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i2c0: i2c@d0011000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0xd0011000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <31>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c1: i2c@d0011100 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0xd0011100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <32>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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};
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};
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