![David Miller](/assets/img/avatar_default.png)
I've been running with this patch on my Niagara2 boxes for some time and have not seen any ill effects yet. Maybe we can stash this into the USB tree to get exposure for some time in -next and if anything crops up we can simply revert? Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
447 lines
12 KiB
C
447 lines
12 KiB
C
/*
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* EHCI HCD (Host Controller Driver) PCI Bus Glue.
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*
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* Copyright (c) 2000-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef CONFIG_PCI
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#error "This file is PCI bus glue. CONFIG_PCI must be defined."
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#endif
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/*-------------------------------------------------------------------------*/
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
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{
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int retval;
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/* we expect static quirk code to handle the "extended capabilities"
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* (currently just BIOS handoff) allowed starting with EHCI 0.96
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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retval = pci_set_mwi(pdev);
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if (!retval)
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ehci_dbg(ehci, "MWI active\n");
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return 0;
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}
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/* called during probe() after chip reset completes */
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static int ehci_pci_setup(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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struct pci_dev *p_smbus;
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u8 rev;
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u32 temp;
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int retval;
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TOSHIBA_2:
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/* celleb's companion chip */
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if (pdev->device == 0x01b5) {
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#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
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ehci->big_endian_mmio = 1;
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#else
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ehci_warn(ehci,
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"unsupported big endian Toshiba quirk\n");
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#endif
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}
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break;
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}
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs +
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HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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/* ehci_init() causes memory for DMA transfers to be
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* allocated. Thus, any vendor-specific workarounds based on
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* limiting the type of memory used for DMA transfers must
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* happen before ehci_init() is called. */
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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DMA_BIT_MASK(31)) < 0)
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ehci_warn(ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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}
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break;
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}
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
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retval = ehci_halt(ehci);
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if (retval)
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return retval;
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/* data structure init */
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retval = ehci_init(hcd);
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if (retval)
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return retval;
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_NEC:
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ehci->need_io_watchdog = 0;
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break;
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case PCI_VENDOR_ID_INTEL:
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ehci->need_io_watchdog = 0;
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if (pdev->device == 0x27cc) {
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ehci->broken_periodic = 1;
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ehci_info(ehci, "using broken periodic workaround\n");
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}
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break;
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case PCI_VENDOR_ID_TDI:
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
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hcd->has_tt = 1;
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tdi_reset(ehci);
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}
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break;
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case PCI_VENDOR_ID_AMD:
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info(ehci, "ignoring AMD8111 (errata)\n");
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retval = -EIO;
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goto done;
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}
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break;
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case PCI_VENDOR_ID_NVIDIA:
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switch (pdev->device) {
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/* Some NForce2 chips have problems with selective suspend;
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* fixed in newer silicon.
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*/
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case 0x0068:
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if (pdev->revision < 0xa4)
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ehci->no_selective_suspend = 1;
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break;
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}
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break;
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case PCI_VENDOR_ID_VIA:
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if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
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u8 tmp;
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/* The VT6212 defaults to a 1 usec EHCI sleep time which
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* hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
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* that sleep time use the conventional 10 usec.
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*/
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pci_read_config_byte(pdev, 0x4b, &tmp);
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if (tmp & 0x20)
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break;
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pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
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}
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break;
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case PCI_VENDOR_ID_ATI:
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/* SB600 and old version of SB700 have a bug in EHCI controller,
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* which causes usb devices lose response in some cases.
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*/
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if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
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p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
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PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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NULL);
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if (!p_smbus)
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break;
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rev = p_smbus->revision;
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if ((pdev->device == 0x4386) || (rev == 0x3a)
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|| (rev == 0x3b)) {
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u8 tmp;
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ehci_info(ehci, "applying AMD SB600/SB700 USB "
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"freeze workaround\n");
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pci_read_config_byte(pdev, 0x53, &tmp);
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pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
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}
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pci_dev_put(p_smbus);
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}
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break;
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}
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = ehci_to_hcd(ehci)->regs + temp;
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temp = ehci_readl(ehci, &ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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ehci_reset(ehci);
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/* at least the Genesys GL880S needs fixup here */
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temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
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temp &= 0x0f;
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if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
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ehci_dbg(ehci, "bogus port configuration: "
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"cc=%d x pcc=%d < ports=%d\n",
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HCS_N_CC(ehci->hcs_params),
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HCS_N_PCC(ehci->hcs_params),
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HCS_N_PORTS(ehci->hcs_params));
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switch (pdev->vendor) {
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case 0x17a0: /* GENESYS */
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/* GL880S: should be PORTS=2 */
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temp |= (ehci->hcs_params & ~0xf);
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ehci->hcs_params = temp;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NF4: should be PCC=10 */
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break;
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}
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}
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/* Serial Bus Release Number is at PCI 0x60 offset */
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* Keep this around for a while just in case some EHCI
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* implementation uses legacy PCI PM support. This test
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* can be removed on 17 Dec 2009 if the dev_warn() hasn't
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* been triggered by then.
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*/
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if (!device_can_wakeup(&pdev->dev)) {
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u16 port_wake;
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pci_read_config_word(pdev, 0x62, &port_wake);
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if (port_wake & 0x0001) {
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dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
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device_set_wakeup_capable(&pdev->dev, 1);
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}
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}
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#ifdef CONFIG_USB_SUSPEND
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/* REVISIT: the controller works fine for wakeup iff the root hub
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* itself is "globally" suspended, but usbcore currently doesn't
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* understand such things.
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*
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* System suspend currently expects to be able to suspend the entire
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* device tree, device-at-a-time. If we failed selective suspend
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* reports, system suspend would fail; so the root hub code must claim
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* success. That's lying to usbcore, and it matters for runtime
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* PM scenarios with selective suspend and remote wakeup...
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*/
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if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
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ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
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#endif
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ehci_port_power(ehci, 1);
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retval = ehci_pci_reinit(ehci, pdev);
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done:
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return retval;
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}
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/*-------------------------------------------------------------------------*/
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#ifdef CONFIG_PM
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/* suspend/resume, section 4.3 */
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/* These routines rely on the PCI bus glue
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* to handle powerdown and wakeup, and currently also on
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* transceivers that don't need any software attention to set up
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* the right sort of wakeup.
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* Also they depend on separate root hub suspend/resume.
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*/
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static int ehci_pci_suspend(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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unsigned long flags;
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int rc = 0;
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if (time_before(jiffies, ehci->next_statechange))
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msleep(10);
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/* Root hub was already suspended. Disable irq emission and
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* mark HW unaccessible, bail out if RH has been resumed. Use
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* the spinlock to properly synchronize with possible pending
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* RH suspend or resume activity.
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*
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* This is still racy as hcd->state is manipulated outside of
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* any locks =P But that will be a different fix.
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*/
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spin_lock_irqsave (&ehci->lock, flags);
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if (hcd->state != HC_STATE_SUSPENDED) {
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rc = -EINVAL;
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goto bail;
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}
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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(void)ehci_readl(ehci, &ehci->regs->intr_enable);
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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bail:
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spin_unlock_irqrestore (&ehci->lock, flags);
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// could save FLADJ in case of Vaux power loss
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// ... we'd only use it to handle clock skew
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return rc;
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}
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static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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// maybe restore FLADJ
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if (time_before(jiffies, ehci->next_statechange))
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msleep(100);
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/* Mark hardware accessible again as we are out of D3 state by now */
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set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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/* If CF is still set and we aren't resuming from hibernation
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* then we maintained PCI Vaux power.
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* Just undo the effect of ehci_pci_suspend().
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*/
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if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
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!hibernated) {
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int mask = INTR_MASK;
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if (!hcd->self.root_hub->do_remote_wakeup)
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mask &= ~STS_PCD;
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ehci_writel(ehci, mask, &ehci->regs->intr_enable);
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ehci_readl(ehci, &ehci->regs->intr_enable);
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return 0;
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}
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usb_root_hub_lost_power(hcd->self.root_hub);
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/* Else reset, to cope with power loss or flush-to-storage
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* style "resume" having let BIOS kick in during reboot.
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*/
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(void) ehci_halt(ehci);
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(void) ehci_reset(ehci);
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(void) ehci_pci_reinit(ehci, pdev);
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/* emptying the schedule aborts any urbs */
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spin_lock_irq(&ehci->lock);
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if (ehci->reclaim)
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end_unlink_async(ehci);
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ehci_work(ehci);
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spin_unlock_irq(&ehci->lock);
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ehci_writel(ehci, ehci->command, &ehci->regs->command);
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ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
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ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
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/* here we "know" root ports should always stay powered */
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ehci_port_power(ehci, 1);
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hcd->state = HC_STATE_SUSPENDED;
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return 0;
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}
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#endif
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static const struct hc_driver ehci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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/*
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* generic hardware linkage
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*/
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.irq = ehci_irq,
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.flags = HCD_MEMORY | HCD_USB2,
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/*
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* basic lifecycle operations
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*/
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.reset = ehci_pci_setup,
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.start = ehci_run,
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#ifdef CONFIG_PM
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.pci_suspend = ehci_pci_suspend,
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.pci_resume = ehci_pci_resume,
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#endif
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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.endpoint_reset = ehci_endpoint_reset,
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/*
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* scheduling support
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*/
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.get_frame_number = ehci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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.relinquish_port = ehci_relinquish_port,
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.port_handed_over = ehci_port_handed_over,
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.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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};
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/*-------------------------------------------------------------------------*/
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids [] = { {
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/* handle any USB 2.0 EHCI controller */
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PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
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.driver_data = (unsigned long) &ehci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver ehci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = usb_hcd_pci_probe,
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.remove = usb_hcd_pci_remove,
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.shutdown = usb_hcd_pci_shutdown,
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#ifdef CONFIG_PM_SLEEP
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.driver = {
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.pm = &usb_hcd_pci_pm_ops
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},
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#endif
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};
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