![]() The DP (display processor) channel disable code tried to busy wait for the DP sync flow end interrupt status bit when disabling the partial plane without a full modeset. That never worked reliably, and it was disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC channel disable" patch, causing ipu_wait_interrupt to always time out after 50 ms, which in turn would trigger a timeout in drm_atomic_helper_wait_for_vblanks. This patch changes ipu_plane_atomic_disable to only queue a DP channel register update at the next frame boundary and set a flag, which can be done without any waiting whatsoever. The imx_drm_atomic_commit_tail then calls a new ipu_plane_disable_deferred function that does the actual IDMAC teardown of the planes that are flagged for deferred disabling, after waiting for the vblank. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> |
||
---|---|---|
.. | ||
dw_hdmi-imx.c | ||
imx-drm-core.c | ||
imx-drm.h | ||
imx-ldb.c | ||
imx-tve.c | ||
ipuv3-crtc.c | ||
ipuv3-plane.c | ||
ipuv3-plane.h | ||
Kconfig | ||
Makefile | ||
parallel-display.c |