![Daniel Vetter](/assets/img/avatar_default.png)
Only when vblanks are supported ofc. Some drivers do this already, but most unfortunately missed it. This opens up bugs after driver load, before the crtc is enabled for the first time. syzbot spotted this when loading vkms as a secondary output. Given how many drivers are buggy it's best to solve this once and for all in shared helper code. Aside from moving the few existing calls to drm_crtc_vblank_reset into helpers (i915 doesn't use helpers, so keeps its own) I think the regression risk is minimal: atomic helpers already rely on drivers calling drm_crtc_vblank_on/off correctly in their hooks when they support vblanks. And driver that's failing to handle vblanks after this is missing those calls already, and vblanks could only work by accident when enabling a CRTC for the first time right after boot. Big thanks to Tetsuo for helping track down what's going wrong here. There's only a few drivers which already had the necessary call and needed some updating: - komeda, atmel and tidss also needed to be changed to call __drm_atomic_helper_crtc_reset() intead of open coding it - tegra and msm even had it in the same place already, just code motion, and malidp already uses __drm_atomic_helper_crtc_reset(). - Laurent noticed that rcar-du and omap open-code their crtc reset and hence would actually be broken by this patch now. So fix them up by reusing the helpers, which brings the drm_crtc_vblank_reset() back. Only call left is in i915, which doesn't use drm_mode_config_reset, but has its own fastboot infrastructure. So that's the only case where we actually want this in the driver still. I've also reviewed all other drivers which set up vblank support with drm_vblank_init. After the previous patch fixing mxsfb all atomic drivers do call drm_crtc_vblank_on/off as they should, the remaining drivers are either legacy kms or legacy dri1 drivers, so not affected by this change to atomic helpers. v2: Use the drm_dev_has_vblank() helper. v3: Laurent pointed out that omap and rcar-du used drm_crtc_vblank_off instead of drm_crtc_vblank_reset. Adjust them too. v4: Laurent noticed that rcar-du and omap open-code their crtc reset and hence would actually be broken by this patch now. So fix them up by reusing the helpers, which brings the drm_crtc_vblank_reset() back. v5: also mention rcar-du and ompadrm in the proper commit message above (Laurent). Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Maxime Ripard <mripard@kernel.org> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://syzkaller.appspot.com/bug?id=0ba17d70d062b2595e1f061231474800f076c7cb Reported-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Reported-by: syzbot+0871b14ca2e2fb64f6e3@syzkaller.appspotmail.com Cc: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp> Cc: "James (Qian) Wang" <james.qian.wang@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Mihail Atanassov <mihail.atanassov@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Ludovic Desroches <ludovic.desroches@microchip.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Jyri Sarha <jsarha@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Emil Velikov <emil.velikov@collabora.com> Cc: zhengbin <zhengbin13@huawei.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-tegra@vger.kernel.org Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-renesas-soc@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200612160056.2082681-1-daniel.vetter@ffwll.ch
849 lines
23 KiB
C
849 lines
23 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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* Author: Rob Clark <rob@ti.com>
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*/
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#include <linux/math64.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_mode.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_vblank.h>
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#include "omap_drv.h"
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#define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
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struct omap_crtc_state {
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/* Must be first. */
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struct drm_crtc_state base;
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/* Shadow values for legacy userspace support. */
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unsigned int rotation;
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unsigned int zpos;
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bool manually_updated;
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};
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#define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
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struct omap_crtc {
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struct drm_crtc base;
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const char *name;
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struct omap_drm_pipeline *pipe;
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enum omap_channel channel;
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struct videomode vm;
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bool ignore_digit_sync_lost;
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bool enabled;
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bool pending;
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wait_queue_head_t pending_wait;
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struct drm_pending_vblank_event *event;
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struct delayed_work update_work;
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void (*framedone_handler)(void *);
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void *framedone_handler_data;
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};
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/* -----------------------------------------------------------------------------
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* Helper Functions
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*/
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struct videomode *omap_crtc_timings(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return &omap_crtc->vm;
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}
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enum omap_channel omap_crtc_channel(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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return omap_crtc->channel;
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}
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static bool omap_crtc_is_pending(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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unsigned long flags;
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bool pending;
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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pending = omap_crtc->pending;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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return pending;
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}
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int omap_crtc_wait_pending(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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/*
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* Timeout is set to a "sufficiently" high value, which should cover
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* a single frame refresh even on slower displays.
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*/
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return wait_event_timeout(omap_crtc->pending_wait,
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!omap_crtc_is_pending(crtc),
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msecs_to_jiffies(250));
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}
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/* -----------------------------------------------------------------------------
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* DSS Manager Functions
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*/
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/*
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* Manager-ops, callbacks from output when they need to configure
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* the upstream part of the video pipe.
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*/
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static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
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enum omap_channel channel)
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{
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priv->dispc_ops->mgr_enable(priv->dispc, channel, true);
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}
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/* Called only from the encoder enable/disable and suspend/resume handlers. */
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static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
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{
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struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
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struct drm_device *dev = crtc->dev;
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struct omap_drm_private *priv = dev->dev_private;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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enum omap_channel channel = omap_crtc->channel;
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struct omap_irq_wait *wait;
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u32 framedone_irq, vsync_irq;
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int ret;
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if (WARN_ON(omap_crtc->enabled == enable))
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return;
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if (omap_state->manually_updated) {
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omap_irq_enable_framedone(crtc, enable);
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omap_crtc->enabled = enable;
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return;
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}
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if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {
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priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
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omap_crtc->enabled = enable;
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return;
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}
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if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
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/*
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* Digit output produces some sync lost interrupts during the
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* first frame when enabling, so we need to ignore those.
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*/
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omap_crtc->ignore_digit_sync_lost = true;
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}
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framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
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channel);
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vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
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if (enable) {
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wait = omap_irq_wait_init(dev, vsync_irq, 1);
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} else {
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/*
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* When we disable the digit output, we need to wait for
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* FRAMEDONE to know that DISPC has finished with the output.
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*
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* OMAP2/3 does not have FRAMEDONE irq for digit output, and in
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* that case we need to use vsync interrupt, and wait for both
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* even and odd frames.
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*/
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if (framedone_irq)
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wait = omap_irq_wait_init(dev, framedone_irq, 1);
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else
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wait = omap_irq_wait_init(dev, vsync_irq, 2);
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}
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priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
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omap_crtc->enabled = enable;
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ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
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if (ret) {
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dev_err(dev->dev, "%s: timeout waiting for %s\n",
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omap_crtc->name, enable ? "enable" : "disable");
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}
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if (omap_crtc->channel == OMAP_DSS_CHANNEL_DIGIT) {
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omap_crtc->ignore_digit_sync_lost = false;
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/* make sure the irq handler sees the value above */
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mb();
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}
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}
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static int omap_crtc_dss_enable(struct omap_drm_private *priv,
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enum omap_channel channel)
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{
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struct drm_crtc *crtc = priv->channels[channel]->crtc;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
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&omap_crtc->vm);
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omap_crtc_set_enabled(&omap_crtc->base, true);
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return 0;
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}
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static void omap_crtc_dss_disable(struct omap_drm_private *priv,
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enum omap_channel channel)
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{
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struct drm_crtc *crtc = priv->channels[channel]->crtc;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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omap_crtc_set_enabled(&omap_crtc->base, false);
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}
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static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
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enum omap_channel channel,
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const struct videomode *vm)
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{
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struct drm_crtc *crtc = priv->channels[channel]->crtc;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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omap_crtc->vm = *vm;
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}
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static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
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enum omap_channel channel,
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const struct dss_lcd_mgr_config *config)
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{
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struct drm_crtc *crtc = priv->channels[channel]->crtc;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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DBG("%s", omap_crtc->name);
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priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
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config);
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}
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static int omap_crtc_dss_register_framedone(
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struct omap_drm_private *priv, enum omap_channel channel,
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void (*handler)(void *), void *data)
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{
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struct drm_crtc *crtc = priv->channels[channel]->crtc;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct drm_device *dev = omap_crtc->base.dev;
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if (omap_crtc->framedone_handler)
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return -EBUSY;
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dev_dbg(dev->dev, "register framedone %s", omap_crtc->name);
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omap_crtc->framedone_handler = handler;
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omap_crtc->framedone_handler_data = data;
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return 0;
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}
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static void omap_crtc_dss_unregister_framedone(
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struct omap_drm_private *priv, enum omap_channel channel,
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void (*handler)(void *), void *data)
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{
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struct drm_crtc *crtc = priv->channels[channel]->crtc;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct drm_device *dev = omap_crtc->base.dev;
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dev_dbg(dev->dev, "unregister framedone %s", omap_crtc->name);
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WARN_ON(omap_crtc->framedone_handler != handler);
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WARN_ON(omap_crtc->framedone_handler_data != data);
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omap_crtc->framedone_handler = NULL;
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omap_crtc->framedone_handler_data = NULL;
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}
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static const struct dss_mgr_ops mgr_ops = {
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.start_update = omap_crtc_dss_start_update,
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.enable = omap_crtc_dss_enable,
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.disable = omap_crtc_dss_disable,
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.set_timings = omap_crtc_dss_set_timings,
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.set_lcd_config = omap_crtc_dss_set_lcd_config,
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.register_framedone_handler = omap_crtc_dss_register_framedone,
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.unregister_framedone_handler = omap_crtc_dss_unregister_framedone,
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};
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/* -----------------------------------------------------------------------------
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* Setup, Flush and Page Flip
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*/
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void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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if (omap_crtc->ignore_digit_sync_lost) {
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irqstatus &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
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if (!irqstatus)
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return;
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}
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DRM_ERROR_RATELIMITED("%s: errors: %08x\n", omap_crtc->name, irqstatus);
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}
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void omap_crtc_vblank_irq(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct drm_device *dev = omap_crtc->base.dev;
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struct omap_drm_private *priv = dev->dev_private;
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bool pending;
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spin_lock(&crtc->dev->event_lock);
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/*
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* If the dispc is busy we're racing the flush operation. Try again on
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* the next vblank interrupt.
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*/
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if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
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spin_unlock(&crtc->dev->event_lock);
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return;
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}
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/* Send the vblank event if one has been requested. */
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if (omap_crtc->event) {
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drm_crtc_send_vblank_event(crtc, omap_crtc->event);
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omap_crtc->event = NULL;
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}
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pending = omap_crtc->pending;
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omap_crtc->pending = false;
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spin_unlock(&crtc->dev->event_lock);
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if (pending)
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drm_crtc_vblank_put(crtc);
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/* Wake up omap_atomic_complete. */
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wake_up(&omap_crtc->pending_wait);
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DBG("%s: apply done", omap_crtc->name);
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}
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void omap_crtc_framedone_irq(struct drm_crtc *crtc, uint32_t irqstatus)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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if (!omap_crtc->framedone_handler)
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return;
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omap_crtc->framedone_handler(omap_crtc->framedone_handler_data);
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spin_lock(&crtc->dev->event_lock);
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/* Send the vblank event if one has been requested. */
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if (omap_crtc->event) {
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drm_crtc_send_vblank_event(crtc, omap_crtc->event);
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omap_crtc->event = NULL;
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}
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omap_crtc->pending = false;
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spin_unlock(&crtc->dev->event_lock);
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/* Wake up omap_atomic_complete. */
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wake_up(&omap_crtc->pending_wait);
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}
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void omap_crtc_flush(struct drm_crtc *crtc)
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{
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
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struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
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if (!omap_state->manually_updated)
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return;
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if (!delayed_work_pending(&omap_crtc->update_work))
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schedule_delayed_work(&omap_crtc->update_work, 0);
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}
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static void omap_crtc_manual_display_update(struct work_struct *data)
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{
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struct omap_crtc *omap_crtc =
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container_of(data, struct omap_crtc, update_work.work);
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struct drm_display_mode *mode = &omap_crtc->pipe->crtc->mode;
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struct omap_dss_device *dssdev = omap_crtc->pipe->output->next;
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struct drm_device *dev = omap_crtc->base.dev;
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const struct omap_dss_driver *dssdrv;
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int ret;
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if (!dssdev) {
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dev_err_once(dev->dev, "missing display dssdev!");
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return;
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}
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dssdrv = dssdev->driver;
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if (!dssdrv || !dssdrv->update) {
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dev_err_once(dev->dev, "missing or incorrect dssdrv!");
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return;
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}
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if (dssdrv->sync)
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dssdrv->sync(dssdev);
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ret = dssdrv->update(dssdev, 0, 0, mode->hdisplay, mode->vdisplay);
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if (ret < 0) {
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spin_lock_irq(&dev->event_lock);
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omap_crtc->pending = false;
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spin_unlock_irq(&dev->event_lock);
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wake_up(&omap_crtc->pending_wait);
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}
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}
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static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
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{
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struct omap_drm_private *priv = crtc->dev->dev_private;
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struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct omap_overlay_manager_info info;
|
|
|
|
memset(&info, 0, sizeof(info));
|
|
|
|
info.default_color = 0x000000;
|
|
info.trans_enabled = false;
|
|
info.partial_alpha_enabled = false;
|
|
info.cpr_enable = false;
|
|
|
|
priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
|
|
}
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* CRTC Functions
|
|
*/
|
|
|
|
static void omap_crtc_destroy(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
|
|
DBG("%s", omap_crtc->name);
|
|
|
|
drm_crtc_cleanup(crtc);
|
|
|
|
kfree(omap_crtc);
|
|
}
|
|
|
|
static void omap_crtc_arm_event(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
|
|
WARN_ON(omap_crtc->pending);
|
|
omap_crtc->pending = true;
|
|
|
|
if (crtc->state->event) {
|
|
omap_crtc->event = crtc->state->event;
|
|
crtc->state->event = NULL;
|
|
}
|
|
}
|
|
|
|
static void omap_crtc_atomic_enable(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *old_state)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct omap_crtc_state *omap_state = to_omap_crtc_state(crtc->state);
|
|
int ret;
|
|
|
|
DBG("%s", omap_crtc->name);
|
|
|
|
priv->dispc_ops->runtime_get(priv->dispc);
|
|
|
|
/* manual updated display will not trigger vsync irq */
|
|
if (omap_state->manually_updated)
|
|
return;
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
drm_crtc_vblank_on(crtc);
|
|
ret = drm_crtc_vblank_get(crtc);
|
|
WARN_ON(ret != 0);
|
|
|
|
omap_crtc_arm_event(crtc);
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
}
|
|
|
|
static void omap_crtc_atomic_disable(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *old_state)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
DBG("%s", omap_crtc->name);
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
if (crtc->state->event) {
|
|
drm_crtc_send_vblank_event(crtc, crtc->state->event);
|
|
crtc->state->event = NULL;
|
|
}
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
|
|
cancel_delayed_work(&omap_crtc->update_work);
|
|
|
|
if (!omap_crtc_wait_pending(crtc))
|
|
dev_warn(dev->dev, "manual display update did not finish!");
|
|
|
|
drm_crtc_vblank_off(crtc);
|
|
|
|
priv->dispc_ops->runtime_put(priv->dispc);
|
|
}
|
|
|
|
static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct videomode vm = {0};
|
|
int r;
|
|
|
|
drm_display_mode_to_videomode(mode, &vm);
|
|
|
|
/*
|
|
* DSI might not call this, since the supplied mode is not a
|
|
* valid DISPC mode. DSI will calculate and configure the
|
|
* proper DISPC mode later.
|
|
*/
|
|
if (omap_crtc->pipe->output->next == NULL ||
|
|
omap_crtc->pipe->output->next->type != OMAP_DISPLAY_TYPE_DSI) {
|
|
r = priv->dispc_ops->mgr_check_timings(priv->dispc,
|
|
omap_crtc->channel,
|
|
&vm);
|
|
if (r)
|
|
return r;
|
|
}
|
|
|
|
/* Check for bandwidth limit */
|
|
if (priv->max_bandwidth) {
|
|
/*
|
|
* Estimation for the bandwidth need of a given mode with one
|
|
* full screen plane:
|
|
* bandwidth = resolution * 32bpp * (pclk / (vtotal * htotal))
|
|
* ^^ Refresh rate ^^
|
|
*
|
|
* The interlaced mode is taken into account by using the
|
|
* pixelclock in the calculation.
|
|
*
|
|
* The equation is rearranged for 64bit arithmetic.
|
|
*/
|
|
uint64_t bandwidth = mode->clock * 1000;
|
|
unsigned int bpp = 4;
|
|
|
|
bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp;
|
|
bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal);
|
|
|
|
/*
|
|
* Reject modes which would need more bandwidth if used with one
|
|
* full resolution plane (most common use case).
|
|
*/
|
|
if (priv->max_bandwidth < bandwidth)
|
|
return MODE_BAD;
|
|
}
|
|
|
|
return MODE_OK;
|
|
}
|
|
|
|
static void omap_crtc_mode_set_nofb(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
|
|
|
|
DBG("%s: set mode: " DRM_MODE_FMT,
|
|
omap_crtc->name, DRM_MODE_ARG(mode));
|
|
|
|
drm_display_mode_to_videomode(mode, &omap_crtc->vm);
|
|
}
|
|
|
|
static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct omap_dss_device *display = omap_crtc->pipe->output->next;
|
|
|
|
if (!display)
|
|
return false;
|
|
|
|
if (display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
|
|
DBG("detected manually updated display!");
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static int omap_crtc_atomic_check(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *state)
|
|
{
|
|
struct drm_plane_state *pri_state;
|
|
|
|
if (state->color_mgmt_changed && state->gamma_lut) {
|
|
unsigned int length = state->gamma_lut->length /
|
|
sizeof(struct drm_color_lut);
|
|
|
|
if (length < 2)
|
|
return -EINVAL;
|
|
}
|
|
|
|
pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary);
|
|
if (pri_state) {
|
|
struct omap_crtc_state *omap_crtc_state =
|
|
to_omap_crtc_state(state);
|
|
|
|
/* Mirror new values for zpos and rotation in omap_crtc_state */
|
|
omap_crtc_state->zpos = pri_state->zpos;
|
|
omap_crtc_state->rotation = pri_state->rotation;
|
|
|
|
/* Check if this CRTC is for a manually updated display */
|
|
omap_crtc_state->manually_updated = omap_crtc_is_manually_updated(crtc);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_crtc_atomic_begin(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *old_crtc_state)
|
|
{
|
|
}
|
|
|
|
static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *old_crtc_state)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
|
|
struct omap_crtc_state *omap_crtc_state = to_omap_crtc_state(crtc->state);
|
|
int ret;
|
|
|
|
if (crtc->state->color_mgmt_changed) {
|
|
struct drm_color_lut *lut = NULL;
|
|
unsigned int length = 0;
|
|
|
|
if (crtc->state->gamma_lut) {
|
|
lut = (struct drm_color_lut *)
|
|
crtc->state->gamma_lut->data;
|
|
length = crtc->state->gamma_lut->length /
|
|
sizeof(*lut);
|
|
}
|
|
priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
|
|
lut, length);
|
|
}
|
|
|
|
omap_crtc_write_crtc_properties(crtc);
|
|
|
|
/* Only flush the CRTC if it is currently enabled. */
|
|
if (!omap_crtc->enabled)
|
|
return;
|
|
|
|
DBG("%s: GO", omap_crtc->name);
|
|
|
|
if (omap_crtc_state->manually_updated) {
|
|
/* send new image for page flips and modeset changes */
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
omap_crtc_flush(crtc);
|
|
omap_crtc_arm_event(crtc);
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
return;
|
|
}
|
|
|
|
ret = drm_crtc_vblank_get(crtc);
|
|
WARN_ON(ret != 0);
|
|
|
|
spin_lock_irq(&crtc->dev->event_lock);
|
|
priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
|
|
omap_crtc_arm_event(crtc);
|
|
spin_unlock_irq(&crtc->dev->event_lock);
|
|
}
|
|
|
|
static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
|
|
struct drm_crtc_state *state,
|
|
struct drm_property *property,
|
|
u64 val)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct drm_plane_state *plane_state;
|
|
|
|
/*
|
|
* Delegate property set to the primary plane. Get the plane state and
|
|
* set the property directly, the shadow copy will be assigned in the
|
|
* omap_crtc_atomic_check callback. This way updates to plane state will
|
|
* always be mirrored in the crtc state correctly.
|
|
*/
|
|
plane_state = drm_atomic_get_plane_state(state->state, crtc->primary);
|
|
if (IS_ERR(plane_state))
|
|
return PTR_ERR(plane_state);
|
|
|
|
if (property == crtc->primary->rotation_property)
|
|
plane_state->rotation = val;
|
|
else if (property == priv->zorder_prop)
|
|
plane_state->zpos = val;
|
|
else
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
|
|
const struct drm_crtc_state *state,
|
|
struct drm_property *property,
|
|
u64 *val)
|
|
{
|
|
struct omap_drm_private *priv = crtc->dev->dev_private;
|
|
struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
|
|
|
|
if (property == crtc->primary->rotation_property)
|
|
*val = omap_state->rotation;
|
|
else if (property == priv->zorder_prop)
|
|
*val = omap_state->zpos;
|
|
else
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void omap_crtc_reset(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc_state *state;
|
|
|
|
if (crtc->state)
|
|
__drm_atomic_helper_crtc_destroy_state(crtc->state);
|
|
|
|
kfree(crtc->state);
|
|
|
|
state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
if (state)
|
|
__drm_atomic_helper_crtc_reset(crtc, &state->base);
|
|
}
|
|
|
|
static struct drm_crtc_state *
|
|
omap_crtc_duplicate_state(struct drm_crtc *crtc)
|
|
{
|
|
struct omap_crtc_state *state, *current_state;
|
|
|
|
if (WARN_ON(!crtc->state))
|
|
return NULL;
|
|
|
|
current_state = to_omap_crtc_state(crtc->state);
|
|
|
|
state = kmalloc(sizeof(*state), GFP_KERNEL);
|
|
if (!state)
|
|
return NULL;
|
|
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
|
|
|
|
state->zpos = current_state->zpos;
|
|
state->rotation = current_state->rotation;
|
|
state->manually_updated = current_state->manually_updated;
|
|
|
|
return &state->base;
|
|
}
|
|
|
|
static const struct drm_crtc_funcs omap_crtc_funcs = {
|
|
.reset = omap_crtc_reset,
|
|
.set_config = drm_atomic_helper_set_config,
|
|
.destroy = omap_crtc_destroy,
|
|
.page_flip = drm_atomic_helper_page_flip,
|
|
.gamma_set = drm_atomic_helper_legacy_gamma_set,
|
|
.atomic_duplicate_state = omap_crtc_duplicate_state,
|
|
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
|
|
.atomic_set_property = omap_crtc_atomic_set_property,
|
|
.atomic_get_property = omap_crtc_atomic_get_property,
|
|
.enable_vblank = omap_irq_enable_vblank,
|
|
.disable_vblank = omap_irq_disable_vblank,
|
|
};
|
|
|
|
static const struct drm_crtc_helper_funcs omap_crtc_helper_funcs = {
|
|
.mode_set_nofb = omap_crtc_mode_set_nofb,
|
|
.atomic_check = omap_crtc_atomic_check,
|
|
.atomic_begin = omap_crtc_atomic_begin,
|
|
.atomic_flush = omap_crtc_atomic_flush,
|
|
.atomic_enable = omap_crtc_atomic_enable,
|
|
.atomic_disable = omap_crtc_atomic_disable,
|
|
.mode_valid = omap_crtc_mode_valid,
|
|
};
|
|
|
|
/* -----------------------------------------------------------------------------
|
|
* Init and Cleanup
|
|
*/
|
|
|
|
static const char *channel_names[] = {
|
|
[OMAP_DSS_CHANNEL_LCD] = "lcd",
|
|
[OMAP_DSS_CHANNEL_DIGIT] = "tv",
|
|
[OMAP_DSS_CHANNEL_LCD2] = "lcd2",
|
|
[OMAP_DSS_CHANNEL_LCD3] = "lcd3",
|
|
};
|
|
|
|
void omap_crtc_pre_init(struct omap_drm_private *priv)
|
|
{
|
|
dss_install_mgr_ops(priv->dss, &mgr_ops, priv);
|
|
}
|
|
|
|
void omap_crtc_pre_uninit(struct omap_drm_private *priv)
|
|
{
|
|
dss_uninstall_mgr_ops(priv->dss);
|
|
}
|
|
|
|
/* initialize crtc */
|
|
struct drm_crtc *omap_crtc_init(struct drm_device *dev,
|
|
struct omap_drm_pipeline *pipe,
|
|
struct drm_plane *plane)
|
|
{
|
|
struct omap_drm_private *priv = dev->dev_private;
|
|
struct drm_crtc *crtc = NULL;
|
|
struct omap_crtc *omap_crtc;
|
|
enum omap_channel channel;
|
|
int ret;
|
|
|
|
channel = pipe->output->dispc_channel;
|
|
|
|
DBG("%s", channel_names[channel]);
|
|
|
|
omap_crtc = kzalloc(sizeof(*omap_crtc), GFP_KERNEL);
|
|
if (!omap_crtc)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
crtc = &omap_crtc->base;
|
|
|
|
init_waitqueue_head(&omap_crtc->pending_wait);
|
|
|
|
omap_crtc->pipe = pipe;
|
|
omap_crtc->channel = channel;
|
|
omap_crtc->name = channel_names[channel];
|
|
|
|
/*
|
|
* We want to refresh manually updated displays from dirty callback,
|
|
* which is called quite often (e.g. for each drawn line). This will
|
|
* be used to do the display update asynchronously to avoid blocking
|
|
* the rendering process and merges multiple dirty calls into one
|
|
* update if they arrive very fast. We also call this function for
|
|
* atomic display updates (e.g. for page flips), which means we do
|
|
* not need extra locking. Atomic updates should be synchronous, but
|
|
* need to wait for the framedone interrupt anyways.
|
|
*/
|
|
INIT_DELAYED_WORK(&omap_crtc->update_work,
|
|
omap_crtc_manual_display_update);
|
|
|
|
ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL,
|
|
&omap_crtc_funcs, NULL);
|
|
if (ret < 0) {
|
|
dev_err(dev->dev, "%s(): could not init crtc for: %s\n",
|
|
__func__, pipe->output->name);
|
|
kfree(omap_crtc);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
drm_crtc_helper_add(crtc, &omap_crtc_helper_funcs);
|
|
|
|
/* The dispc API adapts to what ever size, but the HW supports
|
|
* 256 element gamma table for LCDs and 1024 element table for
|
|
* OMAP_DSS_CHANNEL_DIGIT. X server assumes 256 element gamma
|
|
* tables so lets use that. Size of HW gamma table can be
|
|
* extracted with dispc_mgr_gamma_size(). If it returns 0
|
|
* gamma table is not supported.
|
|
*/
|
|
if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
|
|
unsigned int gamma_lut_size = 256;
|
|
|
|
drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
|
|
drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
|
|
}
|
|
|
|
omap_plane_install_properties(crtc->primary, &crtc->base);
|
|
|
|
return crtc;
|
|
}
|