0f9e03591f
In idle state down clocking the arm cores can result in power savings. Program the power control registers to achieve this and save these registers across a suspend/resume cycle. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
373 lines
16 KiB
C
373 lines
16 KiB
C
/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS4 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <plat/cpu.h>
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#include <mach/map.h>
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#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x))
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#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500)
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#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600)
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#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800)
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#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500)
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#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600)
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#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800)
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#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010)
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#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020)
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#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110)
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#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114)
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#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120)
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#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124)
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#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210)
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#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214)
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#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220)
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#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224)
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#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228)
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#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C)
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#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230)
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#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234)
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#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C)
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#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240)
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#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250)
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#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254)
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#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310)
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#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320)
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#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324)
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#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334)
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#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C)
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#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340)
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#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350)
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#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354)
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#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510)
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#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520)
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#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524)
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#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528)
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#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C)
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#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530)
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#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534)
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#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C)
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#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540)
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#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544)
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#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548)
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#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C)
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#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550)
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#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554)
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#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558)
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#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C)
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#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560)
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#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564)
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#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580)
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#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610)
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#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628)
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#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820)
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#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920)
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#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924)
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#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928)
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#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C)
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#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x0C930) : \
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EXYNOS_CLKREG(0x04930))
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#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930)
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#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930)
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#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934)
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#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940)
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#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C)
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#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950)
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#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x0C960) : \
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EXYNOS_CLKREG(0x08960))
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#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960)
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#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960)
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#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970)
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#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300)
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#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200)
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#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500)
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#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504)
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#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600)
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#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604)
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#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900)
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#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094)
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#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0)
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#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000)
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#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x14004) : \
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EXYNOS_CLKREG(0x10008))
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#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100)
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#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104)
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#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x14108) : \
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EXYNOS_CLKREG(0x10108))
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#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \
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EXYNOS_CLKREG(0x1410C) : \
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EXYNOS_CLKREG(0x1010C))
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#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200)
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#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400)
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#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500)
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#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504)
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#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600)
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#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604)
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#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800)
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#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900)
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#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800)
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#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804)
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#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */
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#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31)
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#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
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#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
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#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31)
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#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31)
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#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29)
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#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16)
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#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0)
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#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4)
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#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8)
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#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12)
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#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16)
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#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20)
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#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24)
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#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)
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#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28
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#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT)
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#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0
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#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT)
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#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4
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#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT)
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#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8
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#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
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#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20)
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#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)
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#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28)
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#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0)
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#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4)
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#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8)
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#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12)
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#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16)
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#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)
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#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24)
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#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)
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#define EXYNOS4_CLKDIV_MFC_SHIFT (0)
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#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0)
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#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4)
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#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8)
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#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12)
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#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16)
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#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20)
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#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24)
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#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0)
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#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)
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#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4)
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#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4)
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#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8)
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#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12)
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#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)
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/* Only for EXYNOS4210 */
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#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238)
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#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338)
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#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538)
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#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938)
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/* Only for EXYNOS4212 */
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#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568)
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#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
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#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
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/* For EXYNOS5250 */
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#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
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#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
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#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
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#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
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#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
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#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
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#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
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#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
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#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
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#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
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#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
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#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
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#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
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#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
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#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
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#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
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#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
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#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
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#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
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#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
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#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
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#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
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#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
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#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
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#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
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#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
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#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
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#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
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#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
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#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
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#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
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#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
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#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
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#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
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#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
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#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
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#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
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#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
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#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
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#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
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#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
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#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
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#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
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#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
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#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
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#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
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#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
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#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
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#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
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#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
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#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
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#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
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#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
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#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
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#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
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#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
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#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
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#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
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#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
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#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
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#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
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#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
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#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
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#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
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#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
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#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
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#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
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#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
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#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
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#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
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#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
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#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
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#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
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#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
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#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
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#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
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#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
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#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
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#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
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#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
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#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
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#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
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#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
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#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
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#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
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#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
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#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
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#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
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#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
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/* Compatibility defines and inclusion */
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#include <mach/regs-pmu.h>
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#define S5P_EPLL_CON EXYNOS4_EPLL_CON0
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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