49ea7fc094
PXA95x isn't widely used. And it adds the effort on supporting multiple platform. So remove it. The assumption is that nobody will miss this support. If you are reading this text because you actually require pxa95x support on a new kernel, we can work out a way to revert this patch or add support to the mmp platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
117 lines
5 KiB
C
117 lines
5 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/irqs.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_IRQS_H
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#define __ASM_MACH_IRQS_H
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#ifdef CONFIG_PXA_HAVE_ISA_IRQS
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#define PXA_ISA_IRQ(x) (x)
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#define PXA_ISA_IRQ_NUM (16)
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#else
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#define PXA_ISA_IRQ_NUM (0)
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#endif
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#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
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#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
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#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
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#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
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#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
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#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
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#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
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#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
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#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
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#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
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#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
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#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
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#define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */
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#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
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#define IRQ_USB PXA_IRQ(11) /* USB Service */
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#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
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#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */
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#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
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#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
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#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
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#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
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#define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */
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#define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */
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#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
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#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
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#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
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#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
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#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
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#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
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#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
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#define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */
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#define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */
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#define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */
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#define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */
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#define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */
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#define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */
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#define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */
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#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
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#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
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#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
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#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
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#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
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#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
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#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
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#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
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#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
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#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */
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#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
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#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
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#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */
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#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
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#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
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#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
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#define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */
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#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
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#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
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#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
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#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
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#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
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#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
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#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
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#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
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#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
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#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
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#define PXA_NR_BUILTIN_GPIO (192)
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#define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x))
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/*
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* The following interrupts are for board specific purposes. Since
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* the kernel can only run on one machine at a time, we can re-use
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* these.
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* By default, no board IRQ is reserved. It should be finished in
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* custom board since sparse IRQ is already enabled.
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*/
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#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO)
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#define PXA_NR_IRQS (IRQ_BOARD_START)
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#ifndef __ASSEMBLY__
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struct irq_data;
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struct pt_regs;
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void pxa_mask_irq(struct irq_data *);
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void pxa_unmask_irq(struct irq_data *);
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void icip_handle_irq(struct pt_regs *);
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void ichp_handle_irq(struct pt_regs *);
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void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int));
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#endif
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#endif /* __ASM_MACH_IRQS_H */
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