![Benjamin Herrenschmidt](/assets/img/avatar_default.png)
The current implementation of lazy interrupts handling has some issues that this tries to address. We don't do the various workarounds we need to do when re-enabling interrupts in some cases such as when returning from an interrupt and thus we may still lose or get delayed decrementer or doorbell interrupts. The current scheme also makes it much harder to handle the external "edge" interrupts provided by some BookE processors when using the EPR facility (External Proxy) and the Freescale Hypervisor. Additionally, we tend to keep interrupts hard disabled in a number of cases, such as decrementer interrupts, external interrupts, or when a masked decrementer interrupt is pending. This is sub-optimal. This is an attempt at fixing it all in one go by reworking the way we do the lazy interrupt disabling from the ground up. The base idea is to replace the "hard_enabled" field with a "irq_happened" field in which we store a bit mask of what interrupt occurred while soft-disabled. When re-enabling, either via arch_local_irq_restore() or when returning from an interrupt, we can now decide what to do by testing bits in that field. We then implement replaying of the missed interrupts either by re-using the existing exception frame (in exception exit case) or via the creation of a new one from an assembly trampoline (in the arch_local_irq_enable case). This removes the need to play with the decrementer to try to create fake interrupts, among others. In addition, this adds a few refinements: - We no longer hard disable decrementer interrupts that occur while soft-disabled. We now simply bump the decrementer back to max (on BookS) or leave it stopped (on BookE) and continue with hard interrupts enabled, which means that we'll potentially get better sample quality from performance monitor interrupts. - Timer, decrementer and doorbell interrupts now hard-enable shortly after removing the source of the interrupt, which means they no longer run entirely hard disabled. Again, this will improve perf sample quality. - On Book3E 64-bit, we now make the performance monitor interrupt act as an NMI like Book3S (the necessary C code for that to work appear to already be present in the FSL perf code, notably calling nmi_enter instead of irq_enter). (This also fixes a bug where BookE perfmon interrupts could clobber r14 ... oops) - We could make "masked" decrementer interrupts act as NMIs when doing timer-based perf sampling to improve the sample quality. Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- v2: - Add hard-enable to decrementer, timer and doorbells - Fix CR clobber in masked irq handling on BookE - Make embedded perf interrupt act as an NMI - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want to retrigger an interrupt without preventing hard-enable v3: - Fix or vs. ori bug on Book3E - Fix enabling of interrupts for some exceptions on Book3E v4: - Fix resend of doorbells on return from interrupt on Book3E v5: - Rebased on top of my latest series, which involves some significant rework of some aspects of the patch. v6: - 32-bit compile fix - more compile fixes with various .config combos - factor out the asm code to soft-disable interrupts - remove the C wrapper around preempt_schedule_irq v7: - Fix a bug with hard irq state tracking on native power7
1067 lines
27 KiB
ArmAsm
1067 lines
27 KiB
ArmAsm
/*
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* This file contains the 64-bit "server" PowerPC variant
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* of the low level exception handling including exception
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* vectors, exception return, part of the slb and stab
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* handling and other fixed offset specific things.
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*
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* This file is meant to be #included from head_64.S due to
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* position dependent assembly.
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*
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* Most of this originates from head_64.S and thus has the same
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* copyright history.
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*
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*/
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#include <asm/hw_irq.h>
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#include <asm/exception-64s.h>
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#include <asm/ptrace.h>
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/*
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* We layout physical memory as follows:
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* 0x0000 - 0x00ff : Secondary processor spin code
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* 0x0100 - 0x2fff : pSeries Interrupt prologs
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* 0x3000 - 0x5fff : interrupt support common interrupt prologs
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* 0x6000 - 0x6fff : Initial (CPU0) segment table
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* 0x7000 - 0x7fff : FWNMI data area
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* 0x8000 - : Early init and support code
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*/
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/*
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* This is the start of the interrupt handlers for pSeries
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* This code runs with relocation off.
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* Code from here to __end_interrupts gets copied down to real
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* address 0x100 when we are running a relocatable kernel.
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* Therefore any relative branches in this section must only
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* branch to labels in this section.
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*/
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. = 0x100
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.globl __start_interrupts
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__start_interrupts:
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.globl system_reset_pSeries;
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system_reset_pSeries:
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HMT_MEDIUM;
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SET_SCRATCH0(r13)
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#ifdef CONFIG_PPC_P7_NAP
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BEGIN_FTR_SECTION
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/* Running native on arch 2.06 or later, check if we are
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* waking up from nap. We only handle no state loss and
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* supervisor state loss. We do -not- handle hypervisor
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* state loss at this time.
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*/
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mfspr r13,SPRN_SRR1
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rlwinm. r13,r13,47-31,30,31
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beq 9f
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/* waking up from powersave (nap) state */
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cmpwi cr1,r13,2
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/* Total loss of HV state is fatal, we could try to use the
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* PIR to locate a PACA, then use an emergency stack etc...
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* but for now, let's just stay stuck here
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*/
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bgt cr1,.
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GET_PACA(r13)
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#ifdef CONFIG_KVM_BOOK3S_64_HV
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lbz r0,PACAPROCSTART(r13)
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cmpwi r0,0x80
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bne 1f
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li r0,1
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stb r0,PACAPROCSTART(r13)
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b kvm_start_guest
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1:
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#endif
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beq cr1,2f
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b .power7_wakeup_noloss
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2: b .power7_wakeup_loss
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9:
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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#endif /* CONFIG_PPC_P7_NAP */
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
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NOTEST, 0x100)
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. = 0x200
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machine_check_pSeries_1:
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/* This is moved out of line as it can be patched by FW, but
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* some code path might still want to branch into the original
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* vector
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*/
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b machine_check_pSeries
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. = 0x300
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.globl data_access_pSeries
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data_access_pSeries:
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HMT_MEDIUM
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SET_SCRATCH0(r13)
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#ifndef CONFIG_POWER4_ONLY
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BEGIN_FTR_SECTION
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b data_access_check_stab
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data_access_not_stab:
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
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#endif
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EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD,
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KVMTEST_PR, 0x300)
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. = 0x380
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.globl data_access_slb_pSeries
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data_access_slb_pSeries:
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HMT_MEDIUM
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SET_SCRATCH0(r13)
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EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
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std r3,PACA_EXSLB+EX_R3(r13)
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mfspr r3,SPRN_DAR
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#ifdef __DISABLED__
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/* Keep that around for when we re-implement dynamic VSIDs */
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cmpdi r3,0
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bge slb_miss_user_pseries
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#endif /* __DISABLED__ */
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mfspr r12,SPRN_SRR1
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#ifndef CONFIG_RELOCATABLE
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b .slb_miss_realmode
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#else
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/*
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* We can't just use a direct branch to .slb_miss_realmode
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* because the distance from here to there depends on where
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* the kernel ends up being put.
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*/
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mfctr r11
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ld r10,PACAKBASE(r13)
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LOAD_HANDLER(r10, .slb_miss_realmode)
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mtctr r10
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bctr
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#endif
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STD_EXCEPTION_PSERIES(0x400, 0x400, instruction_access)
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. = 0x480
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.globl instruction_access_slb_pSeries
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instruction_access_slb_pSeries:
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HMT_MEDIUM
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SET_SCRATCH0(r13)
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EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
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std r3,PACA_EXSLB+EX_R3(r13)
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mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
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#ifdef __DISABLED__
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/* Keep that around for when we re-implement dynamic VSIDs */
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cmpdi r3,0
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bge slb_miss_user_pseries
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#endif /* __DISABLED__ */
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mfspr r12,SPRN_SRR1
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#ifndef CONFIG_RELOCATABLE
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b .slb_miss_realmode
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#else
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mfctr r11
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ld r10,PACAKBASE(r13)
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LOAD_HANDLER(r10, .slb_miss_realmode)
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mtctr r10
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bctr
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#endif
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/* We open code these as we can't have a ". = x" (even with
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* x = "." within a feature section
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*/
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. = 0x500;
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.globl hardware_interrupt_pSeries;
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.globl hardware_interrupt_hv;
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hardware_interrupt_pSeries:
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hardware_interrupt_hv:
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BEGIN_FTR_SECTION
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_MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt,
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EXC_HV, SOFTEN_TEST_HV)
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KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502)
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FTR_SECTION_ELSE
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_MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt,
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EXC_STD, SOFTEN_TEST_HV_201)
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KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500)
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
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STD_EXCEPTION_PSERIES(0x600, 0x600, alignment)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600)
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STD_EXCEPTION_PSERIES(0x700, 0x700, program_check)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x700)
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STD_EXCEPTION_PSERIES(0x800, 0x800, fp_unavailable)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800)
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MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer)
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MASKABLE_EXCEPTION_HV(0x980, 0x982, decrementer)
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STD_EXCEPTION_PSERIES(0xa00, 0xa00, trap_0a)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xa00)
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STD_EXCEPTION_PSERIES(0xb00, 0xb00, trap_0b)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xb00)
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. = 0xc00
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.globl system_call_pSeries
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system_call_pSeries:
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HMT_MEDIUM
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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SET_SCRATCH0(r13)
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GET_PACA(r13)
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std r9,PACA_EXGEN+EX_R9(r13)
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std r10,PACA_EXGEN+EX_R10(r13)
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mfcr r9
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KVMTEST(0xc00)
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GET_SCRATCH0(r13)
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#endif
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BEGIN_FTR_SECTION
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cmpdi r0,0x1ebe
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beq- 1f
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END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
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mr r9,r13
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GET_PACA(r13)
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mfspr r11,SPRN_SRR0
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mfspr r12,SPRN_SRR1
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ld r10,PACAKBASE(r13)
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LOAD_HANDLER(r10, system_call_entry)
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mtspr SPRN_SRR0,r10
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ld r10,PACAKMSR(r13)
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mtspr SPRN_SRR1,r10
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rfid
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b . /* prevent speculative execution */
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KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00)
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/* Fast LE/BE switch system call */
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1: mfspr r12,SPRN_SRR1
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xori r12,r12,MSR_LE
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mtspr SPRN_SRR1,r12
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rfid /* return to userspace */
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b .
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STD_EXCEPTION_PSERIES(0xd00, 0xd00, single_step)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xd00)
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/* At 0xe??? we have a bunch of hypervisor exceptions, we branch
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* out of line to handle them
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*/
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. = 0xe00
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b h_data_storage_hv
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. = 0xe20
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b h_instr_storage_hv
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. = 0xe40
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b emulation_assist_hv
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. = 0xe50
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b hmi_exception_hv
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. = 0xe60
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b hmi_exception_hv
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/* We need to deal with the Altivec unavailable exception
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* here which is at 0xf20, thus in the middle of the
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* prolog code of the PerformanceMonitor one. A little
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* trickery is thus necessary
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*/
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performance_monitor_pSeries_1:
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. = 0xf00
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b performance_monitor_pSeries
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altivec_unavailable_pSeries_1:
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. = 0xf20
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b altivec_unavailable_pSeries
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vsx_unavailable_pSeries_1:
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. = 0xf40
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b vsx_unavailable_pSeries
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#ifdef CONFIG_CBE_RAS
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STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error)
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KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1202)
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#endif /* CONFIG_CBE_RAS */
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STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint)
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KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300)
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#ifdef CONFIG_CBE_RAS
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STD_EXCEPTION_HV(0x1600, 0x1602, cbe_maintenance)
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KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1602)
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#endif /* CONFIG_CBE_RAS */
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STD_EXCEPTION_PSERIES(0x1700, 0x1700, altivec_assist)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x1700)
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#ifdef CONFIG_CBE_RAS
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STD_EXCEPTION_HV(0x1800, 0x1802, cbe_thermal)
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KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0x1802)
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#endif /* CONFIG_CBE_RAS */
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. = 0x3000
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/*** Out of line interrupts support ***/
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/* moved from 0x200 */
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machine_check_pSeries:
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.globl machine_check_fwnmi
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machine_check_fwnmi:
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HMT_MEDIUM
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SET_SCRATCH0(r13) /* save r13 */
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EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common,
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EXC_STD, KVMTEST, 0x200)
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KVM_HANDLER_SKIP(PACA_EXMC, EXC_STD, 0x200)
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#ifndef CONFIG_POWER4_ONLY
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/* moved from 0x300 */
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data_access_check_stab:
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GET_PACA(r13)
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std r9,PACA_EXSLB+EX_R9(r13)
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std r10,PACA_EXSLB+EX_R10(r13)
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mfspr r10,SPRN_DAR
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mfspr r9,SPRN_DSISR
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srdi r10,r10,60
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rlwimi r10,r9,16,0x20
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#ifdef CONFIG_KVM_BOOK3S_PR
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lbz r9,HSTATE_IN_GUEST(r13)
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rlwimi r10,r9,8,0x300
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#endif
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mfcr r9
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cmpwi r10,0x2c
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beq do_stab_bolted_pSeries
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mtcrf 0x80,r9
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ld r9,PACA_EXSLB+EX_R9(r13)
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ld r10,PACA_EXSLB+EX_R10(r13)
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b data_access_not_stab
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do_stab_bolted_pSeries:
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std r11,PACA_EXSLB+EX_R11(r13)
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std r12,PACA_EXSLB+EX_R12(r13)
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GET_SCRATCH0(r10)
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std r10,PACA_EXSLB+EX_R13(r13)
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EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
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#endif /* CONFIG_POWER4_ONLY */
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KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x300)
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KVM_HANDLER_PR_SKIP(PACA_EXSLB, EXC_STD, 0x380)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x400)
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KVM_HANDLER_PR(PACA_EXSLB, EXC_STD, 0x480)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900)
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KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982)
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.align 7
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/* moved from 0xe00 */
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STD_EXCEPTION_HV(., 0xe02, h_data_storage)
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KVM_HANDLER_SKIP(PACA_EXGEN, EXC_HV, 0xe02)
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STD_EXCEPTION_HV(., 0xe22, h_instr_storage)
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KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe22)
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STD_EXCEPTION_HV(., 0xe42, emulation_assist)
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KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe42)
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STD_EXCEPTION_HV(., 0xe62, hmi_exception) /* need to flush cache ? */
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KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe62)
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/* moved from 0xf00 */
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STD_EXCEPTION_PSERIES(., 0xf00, performance_monitor)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf00)
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STD_EXCEPTION_PSERIES(., 0xf20, altivec_unavailable)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf20)
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STD_EXCEPTION_PSERIES(., 0xf40, vsx_unavailable)
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KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40)
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/*
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* An interrupt came in while soft-disabled. We set paca->irq_happened,
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* then, if it was a decrementer interrupt, we bump the dec to max and
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* and return, else we hard disable and return. This is called with
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* r10 containing the value to OR to the paca field.
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*/
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#define MASKED_INTERRUPT(_H) \
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masked_##_H##interrupt: \
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std r11,PACA_EXGEN+EX_R11(r13); \
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lbz r11,PACAIRQHAPPENED(r13); \
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or r11,r11,r10; \
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stb r11,PACAIRQHAPPENED(r13); \
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andi. r10,r10,PACA_IRQ_DEC; \
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beq 1f; \
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lis r10,0x7fff; \
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ori r10,r10,0xffff; \
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mtspr SPRN_DEC,r10; \
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b 2f; \
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1: mfspr r10,SPRN_##_H##SRR1; \
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rldicl r10,r10,48,1; /* clear MSR_EE */ \
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rotldi r10,r10,16; \
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mtspr SPRN_##_H##SRR1,r10; \
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2: mtcrf 0x80,r9; \
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ld r9,PACA_EXGEN+EX_R9(r13); \
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ld r10,PACA_EXGEN+EX_R10(r13); \
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ld r11,PACA_EXGEN+EX_R11(r13); \
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GET_SCRATCH0(r13); \
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##_H##rfid; \
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b .
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MASKED_INTERRUPT()
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MASKED_INTERRUPT(H)
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/*
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* Called from arch_local_irq_enable when an interrupt needs
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* to be resent. r3 contains 0x500 or 0x900 to indicate which
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* kind of interrupt. MSR:EE is already off. We generate a
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* stackframe like if a real interrupt had happened.
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*
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* Note: While MSR:EE is off, we need to make sure that _MSR
|
|
* in the generated frame has EE set to 1 or the exception
|
|
* handler will not properly re-enable them.
|
|
*/
|
|
_GLOBAL(__replay_interrupt)
|
|
/* We are going to jump to the exception common code which
|
|
* will retrieve various register values from the PACA which
|
|
* we don't give a damn about, so we don't bother storing them.
|
|
*/
|
|
mfmsr r12
|
|
mflr r11
|
|
mfcr r9
|
|
ori r12,r12,MSR_EE
|
|
andi. r3,r3,0x0800
|
|
bne decrementer_common
|
|
b hardware_interrupt_common
|
|
|
|
#ifdef CONFIG_PPC_PSERIES
|
|
/*
|
|
* Vectors for the FWNMI option. Share common code.
|
|
*/
|
|
.globl system_reset_fwnmi
|
|
.align 7
|
|
system_reset_fwnmi:
|
|
HMT_MEDIUM
|
|
SET_SCRATCH0(r13) /* save r13 */
|
|
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
|
|
NOTEST, 0x100)
|
|
|
|
#endif /* CONFIG_PPC_PSERIES */
|
|
|
|
#ifdef __DISABLED__
|
|
/*
|
|
* This is used for when the SLB miss handler has to go virtual,
|
|
* which doesn't happen for now anymore but will once we re-implement
|
|
* dynamic VSIDs for shared page tables
|
|
*/
|
|
slb_miss_user_pseries:
|
|
std r10,PACA_EXGEN+EX_R10(r13)
|
|
std r11,PACA_EXGEN+EX_R11(r13)
|
|
std r12,PACA_EXGEN+EX_R12(r13)
|
|
GET_SCRATCH0(r10)
|
|
ld r11,PACA_EXSLB+EX_R9(r13)
|
|
ld r12,PACA_EXSLB+EX_R3(r13)
|
|
std r10,PACA_EXGEN+EX_R13(r13)
|
|
std r11,PACA_EXGEN+EX_R9(r13)
|
|
std r12,PACA_EXGEN+EX_R3(r13)
|
|
clrrdi r12,r13,32
|
|
mfmsr r10
|
|
mfspr r11,SRR0 /* save SRR0 */
|
|
ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
|
|
ori r10,r10,MSR_IR|MSR_DR|MSR_RI
|
|
mtspr SRR0,r12
|
|
mfspr r12,SRR1 /* and SRR1 */
|
|
mtspr SRR1,r10
|
|
rfid
|
|
b . /* prevent spec. execution */
|
|
#endif /* __DISABLED__ */
|
|
|
|
.align 7
|
|
.globl __end_interrupts
|
|
__end_interrupts:
|
|
|
|
/*
|
|
* Code from here down to __end_handlers is invoked from the
|
|
* exception prologs above. Because the prologs assemble the
|
|
* addresses of these handlers using the LOAD_HANDLER macro,
|
|
* which uses an addi instruction, these handlers must be in
|
|
* the first 32k of the kernel image.
|
|
*/
|
|
|
|
/*** Common interrupt handlers ***/
|
|
|
|
STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
|
|
|
|
/*
|
|
* Machine check is different because we use a different
|
|
* save area: PACA_EXMC instead of PACA_EXGEN.
|
|
*/
|
|
.align 7
|
|
.globl machine_check_common
|
|
machine_check_common:
|
|
EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
|
|
FINISH_NAP
|
|
DISABLE_INTS
|
|
bl .save_nvgprs
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .machine_check_exception
|
|
b .ret_from_except
|
|
|
|
STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ)
|
|
STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt)
|
|
STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
|
|
STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
|
|
STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
|
|
STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
|
|
STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
|
|
STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
|
|
STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception)
|
|
STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
|
|
#ifdef CONFIG_ALTIVEC
|
|
STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
|
|
#else
|
|
STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
|
|
#endif
|
|
#ifdef CONFIG_CBE_RAS
|
|
STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
|
|
STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
|
|
STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
|
|
#endif /* CONFIG_CBE_RAS */
|
|
|
|
.align 7
|
|
system_call_entry:
|
|
b system_call_common
|
|
|
|
ppc64_runlatch_on_trampoline:
|
|
b .__ppc64_runlatch_on
|
|
|
|
/*
|
|
* Here we have detected that the kernel stack pointer is bad.
|
|
* R9 contains the saved CR, r13 points to the paca,
|
|
* r10 contains the (bad) kernel stack pointer,
|
|
* r11 and r12 contain the saved SRR0 and SRR1.
|
|
* We switch to using an emergency stack, save the registers there,
|
|
* and call kernel_bad_stack(), which panics.
|
|
*/
|
|
bad_stack:
|
|
ld r1,PACAEMERGSP(r13)
|
|
subi r1,r1,64+INT_FRAME_SIZE
|
|
std r9,_CCR(r1)
|
|
std r10,GPR1(r1)
|
|
std r11,_NIP(r1)
|
|
std r12,_MSR(r1)
|
|
mfspr r11,SPRN_DAR
|
|
mfspr r12,SPRN_DSISR
|
|
std r11,_DAR(r1)
|
|
std r12,_DSISR(r1)
|
|
mflr r10
|
|
mfctr r11
|
|
mfxer r12
|
|
std r10,_LINK(r1)
|
|
std r11,_CTR(r1)
|
|
std r12,_XER(r1)
|
|
SAVE_GPR(0,r1)
|
|
SAVE_GPR(2,r1)
|
|
ld r10,EX_R3(r3)
|
|
std r10,GPR3(r1)
|
|
SAVE_GPR(4,r1)
|
|
SAVE_4GPRS(5,r1)
|
|
ld r9,EX_R9(r3)
|
|
ld r10,EX_R10(r3)
|
|
SAVE_2GPRS(9,r1)
|
|
ld r9,EX_R11(r3)
|
|
ld r10,EX_R12(r3)
|
|
ld r11,EX_R13(r3)
|
|
std r9,GPR11(r1)
|
|
std r10,GPR12(r1)
|
|
std r11,GPR13(r1)
|
|
BEGIN_FTR_SECTION
|
|
ld r10,EX_CFAR(r3)
|
|
std r10,ORIG_GPR3(r1)
|
|
END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
|
|
SAVE_8GPRS(14,r1)
|
|
SAVE_10GPRS(22,r1)
|
|
lhz r12,PACA_TRAP_SAVE(r13)
|
|
std r12,_TRAP(r1)
|
|
addi r11,r1,INT_FRAME_SIZE
|
|
std r11,0(r1)
|
|
li r12,0
|
|
std r12,0(r11)
|
|
ld r2,PACATOC(r13)
|
|
ld r11,exception_marker@toc(r2)
|
|
std r12,RESULT(r1)
|
|
std r11,STACK_FRAME_OVERHEAD-16(r1)
|
|
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .kernel_bad_stack
|
|
b 1b
|
|
|
|
/*
|
|
* Here r13 points to the paca, r9 contains the saved CR,
|
|
* SRR0 and SRR1 are saved in r11 and r12,
|
|
* r9 - r13 are saved in paca->exgen.
|
|
*/
|
|
.align 7
|
|
.globl data_access_common
|
|
data_access_common:
|
|
mfspr r10,SPRN_DAR
|
|
std r10,PACA_EXGEN+EX_DAR(r13)
|
|
mfspr r10,SPRN_DSISR
|
|
stw r10,PACA_EXGEN+EX_DSISR(r13)
|
|
EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
|
|
DISABLE_INTS
|
|
ld r12,_MSR(r1)
|
|
ld r3,PACA_EXGEN+EX_DAR(r13)
|
|
lwz r4,PACA_EXGEN+EX_DSISR(r13)
|
|
li r5,0x300
|
|
b .do_hash_page /* Try to handle as hpte fault */
|
|
|
|
.align 7
|
|
.globl h_data_storage_common
|
|
h_data_storage_common:
|
|
mfspr r10,SPRN_HDAR
|
|
std r10,PACA_EXGEN+EX_DAR(r13)
|
|
mfspr r10,SPRN_HDSISR
|
|
stw r10,PACA_EXGEN+EX_DSISR(r13)
|
|
EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
|
|
bl .save_nvgprs
|
|
DISABLE_INTS
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .unknown_exception
|
|
b .ret_from_except
|
|
|
|
.align 7
|
|
.globl instruction_access_common
|
|
instruction_access_common:
|
|
EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
|
|
DISABLE_INTS
|
|
ld r12,_MSR(r1)
|
|
ld r3,_NIP(r1)
|
|
andis. r4,r12,0x5820
|
|
li r5,0x400
|
|
b .do_hash_page /* Try to handle as hpte fault */
|
|
|
|
STD_EXCEPTION_COMMON(0xe20, h_instr_storage, .unknown_exception)
|
|
|
|
/*
|
|
* Here is the common SLB miss user that is used when going to virtual
|
|
* mode for SLB misses, that is currently not used
|
|
*/
|
|
#ifdef __DISABLED__
|
|
.align 7
|
|
.globl slb_miss_user_common
|
|
slb_miss_user_common:
|
|
mflr r10
|
|
std r3,PACA_EXGEN+EX_DAR(r13)
|
|
stw r9,PACA_EXGEN+EX_CCR(r13)
|
|
std r10,PACA_EXGEN+EX_LR(r13)
|
|
std r11,PACA_EXGEN+EX_SRR0(r13)
|
|
bl .slb_allocate_user
|
|
|
|
ld r10,PACA_EXGEN+EX_LR(r13)
|
|
ld r3,PACA_EXGEN+EX_R3(r13)
|
|
lwz r9,PACA_EXGEN+EX_CCR(r13)
|
|
ld r11,PACA_EXGEN+EX_SRR0(r13)
|
|
mtlr r10
|
|
beq- slb_miss_fault
|
|
|
|
andi. r10,r12,MSR_RI /* check for unrecoverable exception */
|
|
beq- unrecov_user_slb
|
|
mfmsr r10
|
|
|
|
.machine push
|
|
.machine "power4"
|
|
mtcrf 0x80,r9
|
|
.machine pop
|
|
|
|
clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
|
|
mtmsrd r10,1
|
|
|
|
mtspr SRR0,r11
|
|
mtspr SRR1,r12
|
|
|
|
ld r9,PACA_EXGEN+EX_R9(r13)
|
|
ld r10,PACA_EXGEN+EX_R10(r13)
|
|
ld r11,PACA_EXGEN+EX_R11(r13)
|
|
ld r12,PACA_EXGEN+EX_R12(r13)
|
|
ld r13,PACA_EXGEN+EX_R13(r13)
|
|
rfid
|
|
b .
|
|
|
|
slb_miss_fault:
|
|
EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
|
|
ld r4,PACA_EXGEN+EX_DAR(r13)
|
|
li r5,0
|
|
std r4,_DAR(r1)
|
|
std r5,_DSISR(r1)
|
|
b handle_page_fault
|
|
|
|
unrecov_user_slb:
|
|
EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
|
|
DISABLE_INTS
|
|
bl .save_nvgprs
|
|
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .unrecoverable_exception
|
|
b 1b
|
|
|
|
#endif /* __DISABLED__ */
|
|
|
|
|
|
/*
|
|
* r13 points to the PACA, r9 contains the saved CR,
|
|
* r12 contain the saved SRR1, SRR0 is still ready for return
|
|
* r3 has the faulting address
|
|
* r9 - r13 are saved in paca->exslb.
|
|
* r3 is saved in paca->slb_r3
|
|
* We assume we aren't going to take any exceptions during this procedure.
|
|
*/
|
|
_GLOBAL(slb_miss_realmode)
|
|
mflr r10
|
|
#ifdef CONFIG_RELOCATABLE
|
|
mtctr r11
|
|
#endif
|
|
|
|
stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
|
|
std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
|
|
|
|
bl .slb_allocate_realmode
|
|
|
|
/* All done -- return from exception. */
|
|
|
|
ld r10,PACA_EXSLB+EX_LR(r13)
|
|
ld r3,PACA_EXSLB+EX_R3(r13)
|
|
lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
|
|
|
|
mtlr r10
|
|
|
|
andi. r10,r12,MSR_RI /* check for unrecoverable exception */
|
|
beq- 2f
|
|
|
|
.machine push
|
|
.machine "power4"
|
|
mtcrf 0x80,r9
|
|
mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
|
|
.machine pop
|
|
|
|
ld r9,PACA_EXSLB+EX_R9(r13)
|
|
ld r10,PACA_EXSLB+EX_R10(r13)
|
|
ld r11,PACA_EXSLB+EX_R11(r13)
|
|
ld r12,PACA_EXSLB+EX_R12(r13)
|
|
ld r13,PACA_EXSLB+EX_R13(r13)
|
|
rfid
|
|
b . /* prevent speculative execution */
|
|
|
|
2: mfspr r11,SPRN_SRR0
|
|
ld r10,PACAKBASE(r13)
|
|
LOAD_HANDLER(r10,unrecov_slb)
|
|
mtspr SPRN_SRR0,r10
|
|
ld r10,PACAKMSR(r13)
|
|
mtspr SPRN_SRR1,r10
|
|
rfid
|
|
b .
|
|
|
|
unrecov_slb:
|
|
EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
|
|
DISABLE_INTS
|
|
bl .save_nvgprs
|
|
1: addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .unrecoverable_exception
|
|
b 1b
|
|
|
|
|
|
#ifdef CONFIG_PPC_970_NAP
|
|
power4_fixup_nap:
|
|
andc r9,r9,r10
|
|
std r9,TI_LOCAL_FLAGS(r11)
|
|
ld r10,_LINK(r1) /* make idle task do the */
|
|
std r10,_NIP(r1) /* equivalent of a blr */
|
|
blr
|
|
#endif
|
|
|
|
.align 7
|
|
.globl alignment_common
|
|
alignment_common:
|
|
mfspr r10,SPRN_DAR
|
|
std r10,PACA_EXGEN+EX_DAR(r13)
|
|
mfspr r10,SPRN_DSISR
|
|
stw r10,PACA_EXGEN+EX_DSISR(r13)
|
|
EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
|
|
ld r3,PACA_EXGEN+EX_DAR(r13)
|
|
lwz r4,PACA_EXGEN+EX_DSISR(r13)
|
|
std r3,_DAR(r1)
|
|
std r4,_DSISR(r1)
|
|
bl .save_nvgprs
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
ENABLE_INTS
|
|
bl .alignment_exception
|
|
b .ret_from_except
|
|
|
|
.align 7
|
|
.globl program_check_common
|
|
program_check_common:
|
|
EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
|
|
bl .save_nvgprs
|
|
DISABLE_INTS
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .program_check_exception
|
|
b .ret_from_except
|
|
|
|
.align 7
|
|
.globl fp_unavailable_common
|
|
fp_unavailable_common:
|
|
EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
|
|
bne 1f /* if from user, just load it up */
|
|
bl .save_nvgprs
|
|
DISABLE_INTS
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .kernel_fp_unavailable_exception
|
|
BUG_OPCODE
|
|
1: bl .load_up_fpu
|
|
b fast_exception_return
|
|
|
|
.align 7
|
|
.globl altivec_unavailable_common
|
|
altivec_unavailable_common:
|
|
EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
|
|
#ifdef CONFIG_ALTIVEC
|
|
BEGIN_FTR_SECTION
|
|
beq 1f
|
|
bl .load_up_altivec
|
|
b fast_exception_return
|
|
1:
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
|
#endif
|
|
bl .save_nvgprs
|
|
DISABLE_INTS
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .altivec_unavailable_exception
|
|
b .ret_from_except
|
|
|
|
.align 7
|
|
.globl vsx_unavailable_common
|
|
vsx_unavailable_common:
|
|
EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
|
|
#ifdef CONFIG_VSX
|
|
BEGIN_FTR_SECTION
|
|
beq 1f
|
|
b .load_up_vsx
|
|
1:
|
|
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
|
|
#endif
|
|
bl .save_nvgprs
|
|
DISABLE_INTS
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .vsx_unavailable_exception
|
|
b .ret_from_except
|
|
|
|
.align 7
|
|
.globl __end_handlers
|
|
__end_handlers:
|
|
|
|
/*
|
|
* Hash table stuff
|
|
*/
|
|
.align 7
|
|
_STATIC(do_hash_page)
|
|
std r3,_DAR(r1)
|
|
std r4,_DSISR(r1)
|
|
|
|
andis. r0,r4,0xa410 /* weird error? */
|
|
bne- handle_page_fault /* if not, try to insert a HPTE */
|
|
andis. r0,r4,DSISR_DABRMATCH@h
|
|
bne- handle_dabr_fault
|
|
|
|
BEGIN_FTR_SECTION
|
|
andis. r0,r4,0x0020 /* Is it a segment table fault? */
|
|
bne- do_ste_alloc /* If so handle it */
|
|
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
|
|
|
|
clrrdi r11,r1,THREAD_SHIFT
|
|
lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
|
|
andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
|
|
bne 77f /* then don't call hash_page now */
|
|
/*
|
|
* We need to set the _PAGE_USER bit if MSR_PR is set or if we are
|
|
* accessing a userspace segment (even from the kernel). We assume
|
|
* kernel addresses always have the high bit set.
|
|
*/
|
|
rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
|
|
rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
|
|
orc r0,r12,r0 /* MSR_PR | ~high_bit */
|
|
rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
|
|
ori r4,r4,1 /* add _PAGE_PRESENT */
|
|
rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
|
|
|
|
/*
|
|
* r3 contains the faulting address
|
|
* r4 contains the required access permissions
|
|
* r5 contains the trap number
|
|
*
|
|
* at return r3 = 0 for success, 1 for page fault, negative for error
|
|
*/
|
|
bl .hash_page /* build HPTE if possible */
|
|
cmpdi r3,0 /* see if hash_page succeeded */
|
|
|
|
/* Success */
|
|
beq fast_exc_return_irq /* Return from exception on success */
|
|
|
|
/* Error */
|
|
blt- 13f
|
|
|
|
/* Here we have a page fault that hash_page can't handle. */
|
|
handle_page_fault:
|
|
11: ld r4,_DAR(r1)
|
|
ld r5,_DSISR(r1)
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .do_page_fault
|
|
cmpdi r3,0
|
|
beq+ 12f
|
|
bl .save_nvgprs
|
|
mr r5,r3
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
lwz r4,_DAR(r1)
|
|
bl .bad_page_fault
|
|
b .ret_from_except
|
|
|
|
/* We have a data breakpoint exception - handle it */
|
|
handle_dabr_fault:
|
|
bl .save_nvgprs
|
|
ld r4,_DAR(r1)
|
|
ld r5,_DSISR(r1)
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .do_dabr
|
|
12: b .ret_from_except_lite
|
|
|
|
|
|
/* We have a page fault that hash_page could handle but HV refused
|
|
* the PTE insertion
|
|
*/
|
|
13: bl .save_nvgprs
|
|
mr r5,r3
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
ld r4,_DAR(r1)
|
|
bl .low_hash_fault
|
|
b .ret_from_except
|
|
|
|
/*
|
|
* We come here as a result of a DSI at a point where we don't want
|
|
* to call hash_page, such as when we are accessing memory (possibly
|
|
* user memory) inside a PMU interrupt that occurred while interrupts
|
|
* were soft-disabled. We want to invoke the exception handler for
|
|
* the access, or panic if there isn't a handler.
|
|
*/
|
|
77: bl .save_nvgprs
|
|
mr r4,r3
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
li r5,SIGSEGV
|
|
bl .bad_page_fault
|
|
b .ret_from_except
|
|
|
|
/* here we have a segment miss */
|
|
do_ste_alloc:
|
|
bl .ste_allocate /* try to insert stab entry */
|
|
cmpdi r3,0
|
|
bne- handle_page_fault
|
|
b fast_exception_return
|
|
|
|
/*
|
|
* r13 points to the PACA, r9 contains the saved CR,
|
|
* r11 and r12 contain the saved SRR0 and SRR1.
|
|
* r9 - r13 are saved in paca->exslb.
|
|
* We assume we aren't going to take any exceptions during this procedure.
|
|
* We assume (DAR >> 60) == 0xc.
|
|
*/
|
|
.align 7
|
|
_GLOBAL(do_stab_bolted)
|
|
stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
|
|
std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
|
|
|
|
/* Hash to the primary group */
|
|
ld r10,PACASTABVIRT(r13)
|
|
mfspr r11,SPRN_DAR
|
|
srdi r11,r11,28
|
|
rldimi r10,r11,7,52 /* r10 = first ste of the group */
|
|
|
|
/* Calculate VSID */
|
|
/* This is a kernel address, so protovsid = ESID */
|
|
ASM_VSID_SCRAMBLE(r11, r9, 256M)
|
|
rldic r9,r11,12,16 /* r9 = vsid << 12 */
|
|
|
|
/* Search the primary group for a free entry */
|
|
1: ld r11,0(r10) /* Test valid bit of the current ste */
|
|
andi. r11,r11,0x80
|
|
beq 2f
|
|
addi r10,r10,16
|
|
andi. r11,r10,0x70
|
|
bne 1b
|
|
|
|
/* Stick for only searching the primary group for now. */
|
|
/* At least for now, we use a very simple random castout scheme */
|
|
/* Use the TB as a random number ; OR in 1 to avoid entry 0 */
|
|
mftb r11
|
|
rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
|
|
ori r11,r11,0x10
|
|
|
|
/* r10 currently points to an ste one past the group of interest */
|
|
/* make it point to the randomly selected entry */
|
|
subi r10,r10,128
|
|
or r10,r10,r11 /* r10 is the entry to invalidate */
|
|
|
|
isync /* mark the entry invalid */
|
|
ld r11,0(r10)
|
|
rldicl r11,r11,56,1 /* clear the valid bit */
|
|
rotldi r11,r11,8
|
|
std r11,0(r10)
|
|
sync
|
|
|
|
clrrdi r11,r11,28 /* Get the esid part of the ste */
|
|
slbie r11
|
|
|
|
2: std r9,8(r10) /* Store the vsid part of the ste */
|
|
eieio
|
|
|
|
mfspr r11,SPRN_DAR /* Get the new esid */
|
|
clrrdi r11,r11,28 /* Permits a full 32b of ESID */
|
|
ori r11,r11,0x90 /* Turn on valid and kp */
|
|
std r11,0(r10) /* Put new entry back into the stab */
|
|
|
|
sync
|
|
|
|
/* All done -- return from exception. */
|
|
lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
|
|
ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
|
|
|
|
andi. r10,r12,MSR_RI
|
|
beq- unrecov_slb
|
|
|
|
mtcrf 0x80,r9 /* restore CR */
|
|
|
|
mfmsr r10
|
|
clrrdi r10,r10,2
|
|
mtmsrd r10,1
|
|
|
|
mtspr SPRN_SRR0,r11
|
|
mtspr SPRN_SRR1,r12
|
|
ld r9,PACA_EXSLB+EX_R9(r13)
|
|
ld r10,PACA_EXSLB+EX_R10(r13)
|
|
ld r11,PACA_EXSLB+EX_R11(r13)
|
|
ld r12,PACA_EXSLB+EX_R12(r13)
|
|
ld r13,PACA_EXSLB+EX_R13(r13)
|
|
rfid
|
|
b . /* prevent speculative execution */
|
|
|
|
#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
|
|
/*
|
|
* Data area reserved for FWNMI option.
|
|
* This address (0x7000) is fixed by the RPA.
|
|
*/
|
|
.= 0x7000
|
|
.globl fwnmi_data_area
|
|
fwnmi_data_area:
|
|
|
|
/* pseries and powernv need to keep the whole page from
|
|
* 0x7000 to 0x8000 free for use by the firmware
|
|
*/
|
|
. = 0x8000
|
|
#endif /* defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
|
|
|
|
/* Space for CPU0's segment table */
|
|
.balign 4096
|
|
.globl initial_stab
|
|
initial_stab:
|
|
.space 4096
|
|
|
|
#ifdef CONFIG_PPC_POWERNV
|
|
_GLOBAL(opal_mc_secondary_handler)
|
|
HMT_MEDIUM
|
|
SET_SCRATCH0(r13)
|
|
GET_PACA(r13)
|
|
clrldi r3,r3,2
|
|
tovirt(r3,r3)
|
|
std r3,PACA_OPAL_MC_EVT(r13)
|
|
ld r13,OPAL_MC_SRR0(r3)
|
|
mtspr SPRN_SRR0,r13
|
|
ld r13,OPAL_MC_SRR1(r3)
|
|
mtspr SPRN_SRR1,r13
|
|
ld r3,OPAL_MC_GPR3(r3)
|
|
GET_SCRATCH0(r13)
|
|
b machine_check_pSeries
|
|
#endif /* CONFIG_PPC_POWERNV */
|