c74ba8b348
One of the easiest ways to protect the kernel from attack is to reduce the internal attack surface exposed when a "write" flaw is available. By making as much of the kernel read-only as possible, we reduce the attack surface. Many things are written to only during __init, and never changed again. These cannot be made "const" since the compiler will do the wrong thing (we do actually need to write to them). Instead, move these items into a memory region that will be made read-only during mark_rodata_ro() which happens after all kernel __init code has finished. This introduces __ro_after_init as a way to mark such memory, and adds some documentation about the existing __read_mostly marking. This improves the security of the Linux kernel by marking formerly read-write memory regions as read-only on a fully booted up system. Based on work by PaX Team and Brad Spengler. Signed-off-by: Kees Cook <keescook@chromium.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brad Spengler <spender@grsecurity.net> Cc: Brian Gerst <brgerst@gmail.com> Cc: David Brown <david.brown@linaro.org> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: Emese Revfy <re.emese@gmail.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mathias Krause <minipli@googlemail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: PaX Team <pageexec@freemail.hu> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: kernel-hardening@lists.openwall.com Cc: linux-arch <linux-arch@vger.kernel.org> Link: http://lkml.kernel.org/r/1455748879-21872-5-git-send-email-keescook@chromium.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/*
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* include/asm-parisc/cache.h
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*/
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#ifndef __ARCH_PARISC_CACHE_H
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#define __ARCH_PARISC_CACHE_H
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/*
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* PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
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* have 32-byte cachelines. The L1 length appears to be 16 bytes but this
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* is not clearly documented.
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*/
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#define L1_CACHE_BYTES 16
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#define L1_CACHE_SHIFT 4
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#ifndef __ASSEMBLY__
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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/* Read-only memory is marked before mark_rodata_ro() is called. */
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#define __ro_after_init __read_mostly
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void parisc_cache_init(void); /* initializes cache-flushing */
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void disable_sr_hashing_asm(int); /* low level support for above */
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void disable_sr_hashing(void); /* turns off space register hashing */
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void free_sid(unsigned long);
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unsigned long alloc_sid(void);
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struct seq_file;
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extern void show_cache_info(struct seq_file *m);
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extern int split_tlb;
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extern int dcache_stride;
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extern int icache_stride;
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extern struct pdc_cache_info cache_info;
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void parisc_setup_cache_timing(void);
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#define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
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#define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
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#define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
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#endif /* ! __ASSEMBLY__ */
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/* Classes of processor wrt: disabling space register hashing */
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#define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */
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#define SRHASH_PCXL 1 /* pcxl */
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#define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */
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#endif
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