Chen-Yu Tsai d85da227c3 clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM ... The PRCM takes PLL_PERIPH0 as one of its parents for the AR100 clock. As such we need to be able to describe this relationship in the device tree. Export the PLL_PERIPH0 clock so we can reference it in the PRCM node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2017-05-31 21:57:30 +02:00
..
Kconfig	clk: sunxi-ng: enable SUNXI_CCU_MP for PRCM	2017-05-18 08:49:18 +02:00
Makefile	clk: sunxi-ng: add support for PRCM CCUs	2017-04-04 17:43:52 +02:00
ccu-sun5i.c	clk: sunxi-ng: sun5i: Fix mux width for csi clock	2017-03-06 10:25:56 +01:00
ccu-sun5i.h	clk: sunxi-ng: Add sun5i CCU driver	2017-01-23 11:45:29 +01:00
ccu-sun6i-a31.c	clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset	2017-05-14 08:27:17 +02:00
ccu-sun6i-a31.h	clk: sunxi-ng: Add A31/A31s clocks	2016-08-25 22:31:43 +02:00
ccu-sun8i-a23-a33.h	clk: sunxi-ng: Add A33 CCU support	2016-09-10 11:41:19 +02:00
ccu-sun8i-a23.c	clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks	2016-11-11 21:47:36 +01:00
ccu-sun8i-a33.c	Allwinner clock patches for 4.12	2017-04-19 09:02:00 -07:00
ccu-sun8i-h3.c	clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver	2017-03-06 10:25:56 +01:00
ccu-sun8i-h3.h	clk: sunxi-ng: h3: Export PLL_PERIPH0 clock for the PRCM	2017-05-31 21:57:27 +02:00
ccu-sun8i-r.c	clk: sunxi-ng: fix PRCM CCU ir clk parent	2017-04-10 09:04:23 +02:00
ccu-sun8i-r.h	clk: sunxi-ng: fix PRCM CCU CLK_NUMBER value	2017-04-10 09:04:33 +02:00
ccu-sun8i-v3s.c	clk: sunxi-ng: v3s: Fix usb otg device reset bit	2017-05-14 08:27:17 +02:00
ccu-sun8i-v3s.h	clk: sunxi-ng: add support for V3s CCU	2017-01-20 21:39:03 +01:00
ccu-sun9i-a80-de.c	clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR()	2017-02-06 15:01:29 -08:00
ccu-sun9i-a80-de.h	clk: sunxi-ng: Add A80 Display Engine CCU	2017-01-30 08:38:30 +01:00
ccu-sun9i-a80-usb.c	clk: sunxi-ng: Add A80 USB CCU	2017-01-30 08:37:51 +01:00
ccu-sun9i-a80-usb.h	clk: sunxi-ng: Add A80 USB CCU	2017-01-30 08:37:51 +01:00
ccu-sun9i-a80.c	clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code	2017-04-13 14:09:30 +02:00
ccu-sun9i-a80.h	clk: sunxi-ng: Add A80 CCU	2017-01-30 08:37:30 +01:00
ccu-sun50i-a64.c	clk: sunxi-ng: Fix div/mult settings for osc12M on A64	2017-03-20 09:49:43 +01:00
ccu-sun50i-a64.h	clk: sunxi-ng: a64: Export PLL_PERIPH0 clock for the PRCM	2017-05-31 21:57:30 +02:00
ccu_common.c	Allwinner clock patches for 4.12	2017-04-19 09:02:00 -07:00
ccu_common.h	clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocks	2017-04-13 11:22:02 +02:00
ccu_div.c	clk: sunxi-ng: Call divider_round_rate if we only have a single parent	2017-01-27 11:05:34 +01:00
ccu_div.h	clk: sunxi-ng: Implement factors offsets	2017-01-23 11:44:27 +01:00
ccu_frac.c	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_frac.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_gate.c	clk: sunxi-ng: gate: Support common pre-dividers	2017-03-06 10:25:56 +01:00
ccu_gate.h	clk: sunxi-ng: Add gate clock support	2016-07-08 18:04:38 -07:00
ccu_mp.c	clk: sunxi-ng: mp: Adjust parent rate for pre-dividers	2017-03-06 07:36:04 +01:00
ccu_mp.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_mult.c	clk: sunxi-ng: mult: Support PLL lock detection	2017-04-05 09:01:41 +02:00
ccu_mult.h	clk: sunxi-ng: mult: Support PLL lock detection	2017-04-05 09:01:41 +02:00
ccu_mux.c	clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT	2017-01-30 08:36:03 +01:00
ccu_mux.h	clk: sunxi-ng: mux: Add mux table macro	2016-09-10 11:41:18 +02:00
ccu_nk.c	clk: sunxi-ng: use 1 as fallback for minimum multiplier	2017-04-13 14:09:25 +02:00
ccu_nk.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_nkm.c	clk: sunxi-ng: use 1 as fallback for minimum multiplier	2017-04-13 14:09:25 +02:00
ccu_nkm.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_nkmp.c	Allwinner clock changes, take 2	2017-04-21 19:19:46 -07:00
ccu_nkmp.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_nm.c	clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch	2017-04-13 14:09:28 +02:00
ccu_nm.h	clk: sunxi-ng: Rename the internal structures	2016-10-20 19:24:20 +02:00
ccu_phase.c	clk: sunxi-ng: Add phase clock support	2016-07-08 18:04:45 -07:00
ccu_phase.h	clk: sunxi-ng: Add phase clock support	2016-07-08 18:04:45 -07:00
ccu_reset.c	clk: sunxi-ng: Add common infrastructure	2016-07-08 18:04:32 -07:00
ccu_reset.h	clk: sunxi-ng: Add common infrastructure	2016-07-08 18:04:32 -07:00