![]() On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6276/ |
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earlycons.c | ||
irq.c | ||
Makefile | ||
nlm-dma.c | ||
reset.S | ||
smp.c | ||
smpboot.S | ||
time.c |