![Greg Kroah-Hartman](/assets/img/avatar_default.png)
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, __devinitconst, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
1054 lines
25 KiB
C
1054 lines
25 KiB
C
/*
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* linux/drivers/video/mbx/mbxfb.c
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*
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* Copyright (C) 2006-2007 8D Technologies inc
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* Raphael Assenat <raph@8d.com>
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* - Added video overlay support
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* - Various improvements
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*
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* Copyright (C) 2006 Compulab, Ltd.
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* Mike Rapoport <mike@compulab.co.il>
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* - Creation of driver
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*
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* Based on pxafb.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*
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* Intel 2700G (Marathon) Graphics Accelerator Frame Buffer Driver
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*
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*/
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <video/mbxfb.h>
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#include "regs.h"
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#include "reg_bits.h"
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static void __iomem *virt_base_2700;
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#define write_reg(val, reg) do { writel((val), (reg)); } while(0)
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/* Without this delay, the graphics appears somehow scaled and
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* there is a lot of jitter in scanlines. This delay is probably
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* needed only after setting some specific register(s) somewhere,
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* not all over the place... */
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#define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0)
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#define MIN_XRES 16
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#define MIN_YRES 16
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#define MAX_XRES 2048
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#define MAX_YRES 2048
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#define MAX_PALETTES 16
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/* FIXME: take care of different chip revisions with different sizes
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of ODFB */
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#define MEMORY_OFFSET 0x60000
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struct mbxfb_info {
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struct device *dev;
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struct resource *fb_res;
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struct resource *fb_req;
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struct resource *reg_res;
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struct resource *reg_req;
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void __iomem *fb_virt_addr;
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unsigned long fb_phys_addr;
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void __iomem *reg_virt_addr;
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unsigned long reg_phys_addr;
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int (*platform_probe) (struct fb_info * fb);
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int (*platform_remove) (struct fb_info * fb);
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u32 pseudo_palette[MAX_PALETTES];
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#ifdef CONFIG_FB_MBX_DEBUG
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void *debugfs_data;
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#endif
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};
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static struct fb_var_screeninfo mbxfb_default = {
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.xres = 640,
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.yres = 480,
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.xres_virtual = 640,
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.yres_virtual = 480,
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.bits_per_pixel = 16,
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.red = {11, 5, 0},
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.green = {5, 6, 0},
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.blue = {0, 5, 0},
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.activate = FB_ACTIVATE_TEST,
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.height = -1,
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.width = -1,
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.pixclock = 40000,
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.left_margin = 48,
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.right_margin = 16,
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.upper_margin = 33,
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.lower_margin = 10,
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.hsync_len = 96,
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.vsync_len = 2,
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.vmode = FB_VMODE_NONINTERLACED,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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};
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static struct fb_fix_screeninfo mbxfb_fix = {
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.id = "MBX",
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.type = FB_TYPE_PACKED_PIXELS,
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.visual = FB_VISUAL_TRUECOLOR,
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.xpanstep = 0,
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.ypanstep = 0,
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.ywrapstep = 0,
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.accel = FB_ACCEL_NONE,
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};
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struct pixclock_div {
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u8 m;
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u8 n;
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u8 p;
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};
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static unsigned int mbxfb_get_pixclock(unsigned int pixclock_ps,
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struct pixclock_div *div)
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{
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u8 m, n, p;
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unsigned int err = 0;
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unsigned int min_err = ~0x0;
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unsigned int clk;
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unsigned int best_clk = 0;
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unsigned int ref_clk = 13000; /* FIXME: take from platform data */
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unsigned int pixclock;
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/* convert pixclock to KHz */
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pixclock = PICOS2KHZ(pixclock_ps);
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/* PLL output freq = (ref_clk * M) / (N * 2^P)
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*
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* M: 1 to 63
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* N: 1 to 7
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* P: 0 to 7
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*/
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/* RAPH: When N==1, the resulting pixel clock appears to
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* get divided by 2. Preventing N=1 by starting the following
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* loop at 2 prevents this. Is this a bug with my chip
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* revision or something I dont understand? */
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for (m = 1; m < 64; m++) {
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for (n = 2; n < 8; n++) {
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for (p = 0; p < 8; p++) {
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clk = (ref_clk * m) / (n * (1 << p));
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err = (clk > pixclock) ? (clk - pixclock) :
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(pixclock - clk);
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if (err < min_err) {
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min_err = err;
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best_clk = clk;
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div->m = m;
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div->n = n;
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div->p = p;
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}
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}
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}
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}
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return KHZ2PICOS(best_clk);
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}
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static int mbxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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u_int trans, struct fb_info *info)
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{
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u32 val, ret = 1;
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if (regno < MAX_PALETTES) {
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u32 *pal = info->pseudo_palette;
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val = (red & 0xf800) | ((green & 0xfc00) >> 5) |
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((blue & 0xf800) >> 11);
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pal[regno] = val;
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ret = 0;
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}
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return ret;
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}
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static int mbxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
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{
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struct pixclock_div div;
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var->pixclock = mbxfb_get_pixclock(var->pixclock, &div);
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if (var->xres < MIN_XRES)
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var->xres = MIN_XRES;
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if (var->yres < MIN_YRES)
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var->yres = MIN_YRES;
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if (var->xres > MAX_XRES)
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return -EINVAL;
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if (var->yres > MAX_YRES)
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return -EINVAL;
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var->xres_virtual = max(var->xres_virtual, var->xres);
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var->yres_virtual = max(var->yres_virtual, var->yres);
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switch (var->bits_per_pixel) {
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/* 8 bits-per-pixel is not supported yet */
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case 8:
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return -EINVAL;
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case 16:
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var->green.length = (var->green.length == 5) ? 5 : 6;
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var->red.length = 5;
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var->blue.length = 5;
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var->transp.length = 6 - var->green.length;
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var->blue.offset = 0;
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var->green.offset = 5;
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var->red.offset = 5 + var->green.length;
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var->transp.offset = (5 + var->red.offset) & 15;
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break;
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case 24: /* RGB 888 */
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case 32: /* RGBA 8888 */
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var->red.offset = 16;
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var->red.length = 8;
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var->green.offset = 8;
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var->green.length = 8;
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var->blue.offset = 0;
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var->blue.length = 8;
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var->transp.length = var->bits_per_pixel - 24;
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var->transp.offset = (var->transp.length) ? 24 : 0;
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break;
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}
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var->red.msb_right = 0;
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var->green.msb_right = 0;
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var->blue.msb_right = 0;
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var->transp.msb_right = 0;
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return 0;
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}
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static int mbxfb_set_par(struct fb_info *info)
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{
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struct fb_var_screeninfo *var = &info->var;
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struct pixclock_div div;
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ushort hbps, ht, hfps, has;
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ushort vbps, vt, vfps, vas;
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u32 gsctrl = readl(GSCTRL);
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u32 gsadr = readl(GSADR);
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info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
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/* setup color mode */
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gsctrl &= ~(FMsk(GSCTRL_GPIXFMT));
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/* FIXME: add *WORKING* support for 8-bits per color */
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if (info->var.bits_per_pixel == 8) {
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return -EINVAL;
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} else {
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fb_dealloc_cmap(&info->cmap);
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gsctrl &= ~GSCTRL_LUT_EN;
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info->fix.visual = FB_VISUAL_TRUECOLOR;
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switch (info->var.bits_per_pixel) {
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case 16:
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if (info->var.green.length == 5)
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gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
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else
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gsctrl |= GSCTRL_GPIXFMT_RGB565;
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break;
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case 24:
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gsctrl |= GSCTRL_GPIXFMT_RGB888;
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break;
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case 32:
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gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
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break;
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}
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}
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/* setup resolution */
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gsctrl &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
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gsctrl |= Gsctrl_Width(info->var.xres) |
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Gsctrl_Height(info->var.yres);
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write_reg_dly(gsctrl, GSCTRL);
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gsadr &= ~(FMsk(GSADR_SRCSTRIDE));
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gsadr |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel /
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(8 * 16) - 1);
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write_reg_dly(gsadr, GSADR);
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/* setup timings */
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var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
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write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
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Disp_Pll_P(div.p) | DISP_PLL_EN), DISPPLL);
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hbps = var->hsync_len;
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has = hbps + var->left_margin;
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hfps = has + var->xres;
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ht = hfps + var->right_margin;
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vbps = var->vsync_len;
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vas = vbps + var->upper_margin;
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vfps = vas + var->yres;
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vt = vfps + var->lower_margin;
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write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
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write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
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write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
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write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
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write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
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write_reg_dly((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
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write_reg_dly((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
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write_reg_dly((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
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write_reg_dly((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
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write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly(DINTRE_VEVENT0_EN, DINTRE);
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return 0;
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}
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static int mbxfb_blank(int blank, struct fb_info *info)
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{
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switch (blank) {
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case FB_BLANK_POWERDOWN:
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case FB_BLANK_VSYNC_SUSPEND:
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case FB_BLANK_HSYNC_SUSPEND:
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case FB_BLANK_NORMAL:
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write_reg_dly((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
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write_reg_dly((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
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break;
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case FB_BLANK_UNBLANK:
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write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
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break;
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}
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return 0;
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}
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static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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{
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u32 vsctrl, vscadr, vsadr;
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u32 sssize, spoctrl, shctrl;
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u32 vubase, vvbase;
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u32 vovrclk;
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if (set->scaled_width==0 || set->scaled_height==0)
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return -EINVAL;
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/* read registers which have reserved bits
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* so we can write them back as-is. */
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vovrclk = readl(VOVRCLK);
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vsctrl = readl(VSCTRL);
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vscadr = readl(VSCADR);
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vubase = readl(VUBASE);
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vvbase = readl(VVBASE);
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shctrl = readl(SHCTRL);
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spoctrl = readl(SPOCTRL);
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sssize = readl(SSSIZE);
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vsctrl &= ~( FMsk(VSCTRL_VSWIDTH) |
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FMsk(VSCTRL_VSHEIGHT) |
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FMsk(VSCTRL_VPIXFMT) |
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VSCTRL_GAMMA_EN | VSCTRL_CSC_EN |
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VSCTRL_COSITED );
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vsctrl |= Vsctrl_Width(set->width) | Vsctrl_Height(set->height) |
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VSCTRL_CSC_EN;
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vscadr &= ~(VSCADR_STR_EN | FMsk(VSCADR_VBASE_ADR) );
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vubase &= ~(VUBASE_UVHALFSTR | FMsk(VUBASE_UBASE_ADR));
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vvbase &= ~(FMsk(VVBASE_VBASE_ADR));
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switch (set->fmt) {
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case MBXFB_FMT_YUV16:
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vsctrl |= VSCTRL_VPIXFMT_YUV12;
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set->Y_stride = ((set->width) + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_YUV12:
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vsctrl |= VSCTRL_VPIXFMT_YUV12;
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set->Y_stride = ((set->width) + 0xf ) & ~0xf;
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vubase |= VUBASE_UVHALFSTR;
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break;
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case MBXFB_FMT_UY0VY1:
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vsctrl |= VSCTRL_VPIXFMT_UY0VY1;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_VY0UY1:
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vsctrl |= VSCTRL_VPIXFMT_VY0UY1;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_Y0UY1V:
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vsctrl |= VSCTRL_VPIXFMT_Y0UY1V;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_Y0VY1U:
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vsctrl |= VSCTRL_VPIXFMT_Y0VY1U;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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default:
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return -EINVAL;
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}
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/* VSCTRL has the bits which sets the Video Pixel Format.
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* When passing from a packed to planar format,
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* if we write VSCTRL first, VVBASE and VUBASE would
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* be zero if we would not set them here. (And then,
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* the chips hangs and only a reset seems to fix it).
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*
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* If course, the values calculated here have no meaning
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* for packed formats.
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*/
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set->UV_stride = ((set->width/2) + 0x7 ) & ~0x7;
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set->U_offset = set->height * set->Y_stride;
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set->V_offset = set->U_offset +
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set->height * set->UV_stride;
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vubase |= Vubase_Ubase_Adr(
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(0x60000 + set->mem_offset + set->U_offset)>>3);
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vvbase |= Vvbase_Vbase_Adr(
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(0x60000 + set->mem_offset + set->V_offset)>>3);
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vscadr |= Vscadr_Vbase_Adr((0x60000 + set->mem_offset)>>4);
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if (set->enable)
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vscadr |= VSCADR_STR_EN;
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vsadr = Vsadr_Srcstride((set->Y_stride)/16-1) |
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Vsadr_Xstart(set->x) | Vsadr_Ystart(set->y);
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sssize &= ~(FMsk(SSSIZE_SC_WIDTH) | FMsk(SSSIZE_SC_HEIGHT));
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sssize = Sssize_Sc_Width(set->scaled_width-1) |
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Sssize_Sc_Height(set->scaled_height-1);
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spoctrl &= ~(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP |
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SPOCTRL_HV_SC_OR | SPOCTRL_VS_UR_C |
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FMsk(SPOCTRL_VPITCH));
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spoctrl |= Spoctrl_Vpitch((set->height<<11)/set->scaled_height);
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/* Bypass horiz/vert scaler when same size */
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if (set->scaled_width == set->width)
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spoctrl |= SPOCTRL_H_SC_BP;
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if (set->scaled_height == set->height)
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spoctrl |= SPOCTRL_V_SC_BP;
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shctrl &= ~(FMsk(SHCTRL_HPITCH) | SHCTRL_HDECIM);
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shctrl |= Shctrl_Hpitch((set->width<<11)/set->scaled_width);
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/* Video plane registers */
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write_reg(vsctrl, VSCTRL);
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write_reg(vscadr, VSCADR);
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write_reg(vubase, VUBASE);
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write_reg(vvbase, VVBASE);
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write_reg(vsadr, VSADR);
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/* Video scaler registers */
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write_reg(sssize, SSSIZE);
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write_reg(spoctrl, SPOCTRL);
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write_reg(shctrl, SHCTRL);
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/* Clock */
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if (set->enable)
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vovrclk |= 1;
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else
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vovrclk &= ~1;
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write_reg(vovrclk, VOVRCLK);
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return 0;
|
|
}
|
|
|
|
static int mbxfb_ioctl_planeorder(struct mbxfb_planeorder *porder)
|
|
{
|
|
unsigned long gscadr, vscadr;
|
|
|
|
if (porder->bottom == porder->top)
|
|
return -EINVAL;
|
|
|
|
gscadr = readl(GSCADR);
|
|
vscadr = readl(VSCADR);
|
|
|
|
gscadr &= ~(FMsk(GSCADR_BLEND_POS));
|
|
vscadr &= ~(FMsk(VSCADR_BLEND_POS));
|
|
|
|
switch (porder->bottom) {
|
|
case MBXFB_PLANE_GRAPHICS:
|
|
gscadr |= GSCADR_BLEND_GFX;
|
|
break;
|
|
case MBXFB_PLANE_VIDEO:
|
|
vscadr |= VSCADR_BLEND_GFX;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (porder->top) {
|
|
case MBXFB_PLANE_GRAPHICS:
|
|
gscadr |= GSCADR_BLEND_VID;
|
|
break;
|
|
case MBXFB_PLANE_VIDEO:
|
|
vscadr |= GSCADR_BLEND_VID;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
write_reg_dly(vscadr, VSCADR);
|
|
write_reg_dly(gscadr, GSCADR);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static int mbxfb_ioctl_alphactl(struct mbxfb_alphaCtl *alpha)
|
|
{
|
|
unsigned long vscadr, vbbase, vcmsk;
|
|
unsigned long gscadr, gbbase, gdrctrl;
|
|
|
|
vbbase = Vbbase_Glalpha(alpha->overlay_global_alpha) |
|
|
Vbbase_Colkey(alpha->overlay_colorkey);
|
|
|
|
gbbase = Gbbase_Glalpha(alpha->graphics_global_alpha) |
|
|
Gbbase_Colkey(alpha->graphics_colorkey);
|
|
|
|
vcmsk = readl(VCMSK);
|
|
vcmsk &= ~(FMsk(VCMSK_COLKEY_M));
|
|
vcmsk |= Vcmsk_colkey_m(alpha->overlay_colorkey_mask);
|
|
|
|
gdrctrl = readl(GDRCTRL);
|
|
gdrctrl &= ~(FMsk(GDRCTRL_COLKEYM));
|
|
gdrctrl |= Gdrctrl_Colkeym(alpha->graphics_colorkey_mask);
|
|
|
|
vscadr = readl(VSCADR);
|
|
vscadr &= ~(FMsk(VSCADR_BLEND_M) | VSCADR_COLKEYSRC | VSCADR_COLKEY_EN);
|
|
|
|
gscadr = readl(GSCADR);
|
|
gscadr &= ~(FMsk(GSCADR_BLEND_M) | GSCADR_COLKEY_EN | GSCADR_COLKEYSRC);
|
|
|
|
switch (alpha->overlay_colorkey_mode) {
|
|
case MBXFB_COLORKEY_DISABLED:
|
|
break;
|
|
case MBXFB_COLORKEY_PREVIOUS:
|
|
vscadr |= VSCADR_COLKEY_EN;
|
|
break;
|
|
case MBXFB_COLORKEY_CURRENT:
|
|
vscadr |= VSCADR_COLKEY_EN | VSCADR_COLKEYSRC;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (alpha->overlay_blend_mode) {
|
|
case MBXFB_ALPHABLEND_NONE:
|
|
vscadr |= VSCADR_BLEND_NONE;
|
|
break;
|
|
case MBXFB_ALPHABLEND_GLOBAL:
|
|
vscadr |= VSCADR_BLEND_GLOB;
|
|
break;
|
|
case MBXFB_ALPHABLEND_PIXEL:
|
|
vscadr |= VSCADR_BLEND_PIX;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (alpha->graphics_colorkey_mode) {
|
|
case MBXFB_COLORKEY_DISABLED:
|
|
break;
|
|
case MBXFB_COLORKEY_PREVIOUS:
|
|
gscadr |= GSCADR_COLKEY_EN;
|
|
break;
|
|
case MBXFB_COLORKEY_CURRENT:
|
|
gscadr |= GSCADR_COLKEY_EN | GSCADR_COLKEYSRC;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (alpha->graphics_blend_mode) {
|
|
case MBXFB_ALPHABLEND_NONE:
|
|
gscadr |= GSCADR_BLEND_NONE;
|
|
break;
|
|
case MBXFB_ALPHABLEND_GLOBAL:
|
|
gscadr |= GSCADR_BLEND_GLOB;
|
|
break;
|
|
case MBXFB_ALPHABLEND_PIXEL:
|
|
gscadr |= GSCADR_BLEND_PIX;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
write_reg_dly(vbbase, VBBASE);
|
|
write_reg_dly(gbbase, GBBASE);
|
|
write_reg_dly(vcmsk, VCMSK);
|
|
write_reg_dly(gdrctrl, GDRCTRL);
|
|
write_reg_dly(gscadr, GSCADR);
|
|
write_reg_dly(vscadr, VSCADR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct mbxfb_overlaySetup setup;
|
|
struct mbxfb_planeorder porder;
|
|
struct mbxfb_alphaCtl alpha;
|
|
struct mbxfb_reg reg;
|
|
int res;
|
|
__u32 tmp;
|
|
|
|
switch (cmd)
|
|
{
|
|
case MBXFB_IOCX_OVERLAY:
|
|
if (copy_from_user(&setup, (void __user*)arg,
|
|
sizeof(struct mbxfb_overlaySetup)))
|
|
return -EFAULT;
|
|
|
|
res = mbxfb_setupOverlay(&setup);
|
|
if (res)
|
|
return res;
|
|
|
|
if (copy_to_user((void __user*)arg, &setup,
|
|
sizeof(struct mbxfb_overlaySetup)))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
|
|
case MBXFB_IOCS_PLANEORDER:
|
|
if (copy_from_user(&porder, (void __user*)arg,
|
|
sizeof(struct mbxfb_planeorder)))
|
|
return -EFAULT;
|
|
|
|
return mbxfb_ioctl_planeorder(&porder);
|
|
|
|
case MBXFB_IOCS_ALPHA:
|
|
if (copy_from_user(&alpha, (void __user*)arg,
|
|
sizeof(struct mbxfb_alphaCtl)))
|
|
return -EFAULT;
|
|
|
|
return mbxfb_ioctl_alphactl(&alpha);
|
|
|
|
case MBXFB_IOCS_REG:
|
|
if (copy_from_user(®, (void __user*)arg,
|
|
sizeof(struct mbxfb_reg)))
|
|
return -EFAULT;
|
|
|
|
if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */
|
|
return -EINVAL;
|
|
|
|
tmp = readl(virt_base_2700 + reg.addr);
|
|
tmp &= ~reg.mask;
|
|
tmp |= reg.val & reg.mask;
|
|
writel(tmp, virt_base_2700 + reg.addr);
|
|
|
|
return 0;
|
|
case MBXFB_IOCX_REG:
|
|
if (copy_from_user(®, (void __user*)arg,
|
|
sizeof(struct mbxfb_reg)))
|
|
return -EFAULT;
|
|
|
|
if (reg.addr >= 0x10000) /* regs are from 0x3fe0000 to 0x3feffff */
|
|
return -EINVAL;
|
|
reg.val = readl(virt_base_2700 + reg.addr);
|
|
|
|
if (copy_to_user((void __user*)arg, ®,
|
|
sizeof(struct mbxfb_reg)))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static struct fb_ops mbxfb_ops = {
|
|
.owner = THIS_MODULE,
|
|
.fb_check_var = mbxfb_check_var,
|
|
.fb_set_par = mbxfb_set_par,
|
|
.fb_setcolreg = mbxfb_setcolreg,
|
|
.fb_fillrect = cfb_fillrect,
|
|
.fb_copyarea = cfb_copyarea,
|
|
.fb_imageblit = cfb_imageblit,
|
|
.fb_blank = mbxfb_blank,
|
|
.fb_ioctl = mbxfb_ioctl,
|
|
};
|
|
|
|
/*
|
|
Enable external SDRAM controller. Assume that all clocks are active
|
|
by now.
|
|
*/
|
|
static void setup_memc(struct fb_info *fbi)
|
|
{
|
|
unsigned long tmp;
|
|
int i;
|
|
|
|
/* FIXME: use platform specific parameters */
|
|
/* setup SDRAM controller */
|
|
write_reg_dly((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
|
|
LMCFG_LMA_TS),
|
|
LMCFG);
|
|
|
|
write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
|
|
|
|
/* setup SDRAM timings */
|
|
write_reg_dly((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
|
|
Lmtim_Trc(9) | Lmtim_Tdpl(2)),
|
|
LMTIM);
|
|
/* setup SDRAM refresh rate */
|
|
write_reg_dly(0xc2b, LMREFRESH);
|
|
/* setup SDRAM type parameters */
|
|
write_reg_dly((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
|
|
LMTYPE_COLSZ_8),
|
|
LMTYPE);
|
|
/* enable memory controller */
|
|
write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
|
|
/* perform dummy reads */
|
|
for ( i = 0; i < 16; i++ ) {
|
|
tmp = readl(fbi->screen_base);
|
|
}
|
|
}
|
|
|
|
static void enable_clocks(struct fb_info *fbi)
|
|
{
|
|
/* enable clocks */
|
|
write_reg_dly(SYSCLKSRC_PLL_2, SYSCLKSRC);
|
|
write_reg_dly(PIXCLKSRC_PLL_1, PIXCLKSRC);
|
|
write_reg_dly(0x00000000, CLKSLEEP);
|
|
|
|
/* PLL output = (Frefclk * M) / (N * 2^P )
|
|
*
|
|
* M: 0x17, N: 0x3, P: 0x0 == 100 Mhz!
|
|
* M: 0xb, N: 0x1, P: 0x1 == 71 Mhz
|
|
* */
|
|
write_reg_dly((Core_Pll_M(0xb) | Core_Pll_N(0x1) | Core_Pll_P(0x1) |
|
|
CORE_PLL_EN),
|
|
COREPLL);
|
|
|
|
write_reg_dly((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
|
|
DISP_PLL_EN),
|
|
DISPPLL);
|
|
|
|
write_reg_dly(0x00000000, VOVRCLK);
|
|
write_reg_dly(PIXCLK_EN, PIXCLK);
|
|
write_reg_dly(MEMCLK_EN, MEMCLK);
|
|
write_reg_dly(0x00000001, M24CLK);
|
|
write_reg_dly(0x00000001, MBXCLK);
|
|
write_reg_dly(SDCLK_EN, SDCLK);
|
|
write_reg_dly(0x00000001, PIXCLKDIV);
|
|
}
|
|
|
|
static void setup_graphics(struct fb_info *fbi)
|
|
{
|
|
unsigned long gsctrl;
|
|
unsigned long vscadr;
|
|
|
|
gsctrl = GSCTRL_GAMMA_EN | Gsctrl_Width(fbi->var.xres) |
|
|
Gsctrl_Height(fbi->var.yres);
|
|
switch (fbi->var.bits_per_pixel) {
|
|
case 16:
|
|
if (fbi->var.green.length == 5)
|
|
gsctrl |= GSCTRL_GPIXFMT_ARGB1555;
|
|
else
|
|
gsctrl |= GSCTRL_GPIXFMT_RGB565;
|
|
break;
|
|
case 24:
|
|
gsctrl |= GSCTRL_GPIXFMT_RGB888;
|
|
break;
|
|
case 32:
|
|
gsctrl |= GSCTRL_GPIXFMT_ARGB8888;
|
|
break;
|
|
}
|
|
|
|
write_reg_dly(gsctrl, GSCTRL);
|
|
write_reg_dly(0x00000000, GBBASE);
|
|
write_reg_dly(0x00ffffff, GDRCTRL);
|
|
write_reg_dly((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
|
|
write_reg_dly(0x00000000, GPLUT);
|
|
|
|
vscadr = readl(VSCADR);
|
|
vscadr &= ~(FMsk(VSCADR_BLEND_POS) | FMsk(VSCADR_BLEND_M));
|
|
vscadr |= VSCADR_BLEND_VID | VSCADR_BLEND_NONE;
|
|
write_reg_dly(vscadr, VSCADR);
|
|
}
|
|
|
|
static void setup_display(struct fb_info *fbi)
|
|
{
|
|
unsigned long dsctrl = 0;
|
|
|
|
dsctrl = DSCTRL_BLNK_POL;
|
|
if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
|
|
dsctrl |= DSCTRL_HS_POL;
|
|
if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
|
|
dsctrl |= DSCTRL_VS_POL;
|
|
write_reg_dly(dsctrl, DSCTRL);
|
|
write_reg_dly(0xd0303010, DMCTRL);
|
|
write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
|
|
}
|
|
|
|
static void enable_controller(struct fb_info *fbi)
|
|
{
|
|
u32 svctrl, shctrl;
|
|
|
|
write_reg_dly(SYSRST_RST, SYSRST);
|
|
|
|
/* setup a timeout, raise drive strength */
|
|
write_reg_dly(0xffffff0c, SYSCFG);
|
|
|
|
enable_clocks(fbi);
|
|
setup_memc(fbi);
|
|
setup_graphics(fbi);
|
|
setup_display(fbi);
|
|
|
|
shctrl = readl(SHCTRL);
|
|
shctrl &= ~(FMsk(SHCTRL_HINITIAL));
|
|
shctrl |= Shctrl_Hinitial(4<<11);
|
|
writel(shctrl, SHCTRL);
|
|
|
|
svctrl = Svctrl_Initial1(1<<10) | Svctrl_Initial2(1<<10);
|
|
writel(svctrl, SVCTRL);
|
|
|
|
writel(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP | SPOCTRL_VORDER_4TAP
|
|
, SPOCTRL);
|
|
|
|
/* Those coefficients are good for scaling up. For scaling
|
|
* down, the application has to calculate them. */
|
|
write_reg(0xff000100, VSCOEFF0);
|
|
write_reg(0xfdfcfdfe, VSCOEFF1);
|
|
write_reg(0x170d0500, VSCOEFF2);
|
|
write_reg(0x3d372d22, VSCOEFF3);
|
|
write_reg(0x00000040, VSCOEFF4);
|
|
|
|
write_reg(0xff010100, HSCOEFF0);
|
|
write_reg(0x00000000, HSCOEFF1);
|
|
write_reg(0x02010000, HSCOEFF2);
|
|
write_reg(0x01020302, HSCOEFF3);
|
|
write_reg(0xf9fbfe00, HSCOEFF4);
|
|
write_reg(0xfbf7f6f7, HSCOEFF5);
|
|
write_reg(0x1c110700, HSCOEFF6);
|
|
write_reg(0x3e393127, HSCOEFF7);
|
|
write_reg(0x00000040, HSCOEFF8);
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
/*
|
|
* Power management hooks. Note that we won't be called from IRQ context,
|
|
* unlike the blank functions above, so we may sleep.
|
|
*/
|
|
static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
/* make frame buffer memory enter self-refresh mode */
|
|
write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);
|
|
while (readl(LMPWRSTAT) != LMPWRSTAT_MC_PWR_SRM)
|
|
; /* empty statement */
|
|
|
|
/* reset the device, since it's initial state is 'mostly sleeping' */
|
|
write_reg_dly(SYSRST_RST, SYSRST);
|
|
return 0;
|
|
}
|
|
|
|
static int mbxfb_resume(struct platform_device *dev)
|
|
{
|
|
struct fb_info *fbi = platform_get_drvdata(dev);
|
|
|
|
enable_clocks(fbi);
|
|
/* setup_graphics(fbi); */
|
|
/* setup_display(fbi); */
|
|
|
|
write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
|
|
return 0;
|
|
}
|
|
#else
|
|
#define mbxfb_suspend NULL
|
|
#define mbxfb_resume NULL
|
|
#endif
|
|
|
|
/* debugfs entries */
|
|
#ifndef CONFIG_FB_MBX_DEBUG
|
|
#define mbxfb_debugfs_init(x) do {} while(0)
|
|
#define mbxfb_debugfs_remove(x) do {} while(0)
|
|
#endif
|
|
|
|
#define res_size(_r) (((_r)->end - (_r)->start) + 1)
|
|
|
|
static int mbxfb_probe(struct platform_device *dev)
|
|
{
|
|
int ret;
|
|
struct fb_info *fbi;
|
|
struct mbxfb_info *mfbi;
|
|
struct mbxfb_platform_data *pdata;
|
|
|
|
dev_dbg(&dev->dev, "mbxfb_probe\n");
|
|
|
|
pdata = dev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&dev->dev, "platform data is required\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
|
|
if (fbi == NULL) {
|
|
dev_err(&dev->dev, "framebuffer_alloc failed\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
mfbi = fbi->par;
|
|
fbi->pseudo_palette = mfbi->pseudo_palette;
|
|
|
|
|
|
if (pdata->probe)
|
|
mfbi->platform_probe = pdata->probe;
|
|
if (pdata->remove)
|
|
mfbi->platform_remove = pdata->remove;
|
|
|
|
mfbi->fb_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
|
|
mfbi->reg_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
|
|
|
|
if (!mfbi->fb_res || !mfbi->reg_res) {
|
|
dev_err(&dev->dev, "no resources found\n");
|
|
ret = -ENODEV;
|
|
goto err1;
|
|
}
|
|
|
|
mfbi->fb_req = request_mem_region(mfbi->fb_res->start,
|
|
res_size(mfbi->fb_res), dev->name);
|
|
if (mfbi->fb_req == NULL) {
|
|
dev_err(&dev->dev, "failed to claim framebuffer memory\n");
|
|
ret = -EINVAL;
|
|
goto err1;
|
|
}
|
|
mfbi->fb_phys_addr = mfbi->fb_res->start;
|
|
|
|
mfbi->reg_req = request_mem_region(mfbi->reg_res->start,
|
|
res_size(mfbi->reg_res), dev->name);
|
|
if (mfbi->reg_req == NULL) {
|
|
dev_err(&dev->dev, "failed to claim Marathon registers\n");
|
|
ret = -EINVAL;
|
|
goto err2;
|
|
}
|
|
mfbi->reg_phys_addr = mfbi->reg_res->start;
|
|
|
|
mfbi->reg_virt_addr = devm_ioremap_nocache(&dev->dev,
|
|
mfbi->reg_phys_addr,
|
|
res_size(mfbi->reg_req));
|
|
if (!mfbi->reg_virt_addr) {
|
|
dev_err(&dev->dev, "failed to ioremap Marathon registers\n");
|
|
ret = -EINVAL;
|
|
goto err3;
|
|
}
|
|
virt_base_2700 = mfbi->reg_virt_addr;
|
|
|
|
mfbi->fb_virt_addr = devm_ioremap_nocache(&dev->dev, mfbi->fb_phys_addr,
|
|
res_size(mfbi->fb_req));
|
|
if (!mfbi->fb_virt_addr) {
|
|
dev_err(&dev->dev, "failed to ioremap frame buffer\n");
|
|
ret = -EINVAL;
|
|
goto err3;
|
|
}
|
|
|
|
fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000);
|
|
fbi->screen_size = pdata->memsize;
|
|
fbi->fbops = &mbxfb_ops;
|
|
|
|
fbi->var = mbxfb_default;
|
|
fbi->fix = mbxfb_fix;
|
|
fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
|
|
fbi->fix.smem_len = pdata->memsize;
|
|
fbi->fix.line_length = mbxfb_default.xres_virtual *
|
|
mbxfb_default.bits_per_pixel / 8;
|
|
|
|
ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
|
|
if (ret < 0) {
|
|
dev_err(&dev->dev, "fb_alloc_cmap failed\n");
|
|
ret = -EINVAL;
|
|
goto err3;
|
|
}
|
|
|
|
platform_set_drvdata(dev, fbi);
|
|
|
|
printk(KERN_INFO "fb%d: mbx frame buffer device\n", fbi->node);
|
|
|
|
if (mfbi->platform_probe)
|
|
mfbi->platform_probe(fbi);
|
|
|
|
enable_controller(fbi);
|
|
|
|
mbxfb_debugfs_init(fbi);
|
|
|
|
ret = register_framebuffer(fbi);
|
|
if (ret < 0) {
|
|
dev_err(&dev->dev, "register_framebuffer failed\n");
|
|
ret = -EINVAL;
|
|
goto err6;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err6:
|
|
fb_dealloc_cmap(&fbi->cmap);
|
|
err3:
|
|
release_mem_region(mfbi->reg_res->start, res_size(mfbi->reg_res));
|
|
err2:
|
|
release_mem_region(mfbi->fb_res->start, res_size(mfbi->fb_res));
|
|
err1:
|
|
framebuffer_release(fbi);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mbxfb_remove(struct platform_device *dev)
|
|
{
|
|
struct fb_info *fbi = platform_get_drvdata(dev);
|
|
|
|
write_reg_dly(SYSRST_RST, SYSRST);
|
|
|
|
mbxfb_debugfs_remove(fbi);
|
|
|
|
if (fbi) {
|
|
struct mbxfb_info *mfbi = fbi->par;
|
|
|
|
unregister_framebuffer(fbi);
|
|
if (mfbi) {
|
|
if (mfbi->platform_remove)
|
|
mfbi->platform_remove(fbi);
|
|
|
|
|
|
if (mfbi->reg_req)
|
|
release_mem_region(mfbi->reg_req->start,
|
|
res_size(mfbi->reg_req));
|
|
if (mfbi->fb_req)
|
|
release_mem_region(mfbi->fb_req->start,
|
|
res_size(mfbi->fb_req));
|
|
}
|
|
framebuffer_release(fbi);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver mbxfb_driver = {
|
|
.probe = mbxfb_probe,
|
|
.remove = mbxfb_remove,
|
|
.suspend = mbxfb_suspend,
|
|
.resume = mbxfb_resume,
|
|
.driver = {
|
|
.name = "mbx-fb",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mbxfb_driver);
|
|
|
|
MODULE_DESCRIPTION("loadable framebuffer driver for Marathon device");
|
|
MODULE_AUTHOR("Mike Rapoport, Compulab");
|
|
MODULE_LICENSE("GPL");
|