40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
Mixel LVDS PHY
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This LVDS PHY supports two LVDS channels.
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Required properties:
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- compatible: must be "mixel,lvds-phy".
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- reg: offset and length of the register block.
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- #address-cells: number of address cells for the LVDS channel subnodes, must
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be <1>.
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- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>.
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- clocks: clock phandle and specifier pair.
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- clock-names: string, clock input name, must be "phy".
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- power-domains: phandle pointing to power domain.
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The LVDS PHY device tree node should have the subnodes corresponding to the two
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LVDS channels. These subnodes must contain the following properties:
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- reg: the PHY ID.
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- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
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Example:
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ldb_phy@56241000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mixel,lvds-phy";
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reg = <0x0 0x56241000 0x0 0x100>;
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clocks = <&clk IMX_LVDS0_PHY_CLK>;
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clock-names = "phy";
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power-domains = <&pd IMX_SC_R_LVDS_0>;
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ldb1_phy1: port@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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ldb1_phy2: port@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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