61 lines
1.4 KiB
Plaintext
61 lines
1.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include "imx8dxl-evk-enet0.dts"
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ðphy1 {
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status = "disabled";
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};
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&fec1 {
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pinctrl-0 = <&pinctrl_fec1_rmii>;
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clocks = <&enet0_lpcg 4>,
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<&enet0_lpcg 2>,
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<&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>,
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<&enet0_lpcg 0>,
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<&enet0_lpcg 1>;
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phy-mode = "rmii";
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phy-handle = <ðphy2>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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tja110x,refclk_in;
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};
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};
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};
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&iomuxc {
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pinctrl_fec1_rmii: fec1rmiigrp {
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fsl,pins = <
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IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
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IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
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IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
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IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
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IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000060
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IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
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IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
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IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
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IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
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IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
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IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
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IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000060
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>;
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};
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};
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&max7322 {
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status = "disabled";
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};
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®_fec1_io {
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status = "disabled";
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};
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