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alistair23-linux/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mn.dtsi"
/ {
model = "NXP i.MX8MNano DDR4 EVK board";
compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
status {
label = "status";
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
reset-post-delay-ms = <40>;
#reset-cells = <0>;
};
usdhc1_pwrseq: usdhc1_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_gpio>;
reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay-us = <12000>;
enable-active-high;
};
reg_audio_board: regulator-audio-board {
compatible = "regulator-fixed";
regulator-name = "EXT_PWREN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
startup-delay-us = <300000>;
gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>;
};
wm8524: audio-codec {
#sound-dai-cells = <0>;
compatible = "wlf,wm8524";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_wlf>;
wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
clock-names = "mclk";
};
sound-wm8524 {
compatible = "fsl,imx-audio-wm8524";
model = "wm8524-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8524>;
audio-routing =
"Line Out Jack", "LINEVOUTL",
"Line Out Jack", "LINEVOUTR";
asrc-controller = <&easrc>;
};
sound-micfil {
compatible = "fsl,imx-audio-micfil";
model = "imx-audio-micfil";
cpu-dai = <&micfil>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
sound-ak5558 {
compatible = "fsl,imx-audio-ak5558";
model = "ak5558-audio";
audio-cpu = <&sai5>;
audio-codec = <&ak5558>;
status = "disabled";
};
};
&clk {
assigned-clocks = <&clk IMX8MN_AUDIO_PLL1>, <&clk IMX8MN_AUDIO_PLL2>;
assigned-clock-rates = <393216000>, <361267200>;
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&iomuxc {
pinctrl-names = "default";
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
>;
};
pinctrl_mipi_dsi_en: mipi_dsi_en {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
>;
};
pinctrl_gpio_wlf: gpiowlfgrp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c2_gpio: i2c2grp-gpio {
fsl,pins = <
MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
>;
};
pinctrl_i2c3_gpio: i2c3grp-gpio {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
>;
};
pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6
MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6
MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6
MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6
MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6
MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6
MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
>;
};
pinctrl_usdhc1_gpio: usdhc1grpgpio {
fsl,pins = <
MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111
>;
};
pinctrl_csi_pwn: csi_pwn_grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
>;
};
pinctrl_csi_rst: csi_rst_grp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
adv_bridge: adv7535@3d {
compatible = "adi,adv7533";
reg = <0x3d>;
adi,addr-cec = <0x3b>;
adi,dsi-lanes = <4>;
status = "okay";
port {
adv7535_from_dsim: endpoint {
remote-endpoint = <&dsim_to_adv7535>;
};
};
};
ptn5110_1: tcpc@50 {
compatible = "nxp,ptn5110";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
interrupt-parent = <&gpio2>;
interrupts = <11 8>;
status = "okay";
port {
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
ak4458_1: ak4458@10 {
compatible = "asahi-kasei,ak4458";
reg = <0x10>;
AVDD-supply = <&reg_audio_board>;
DVDD-supply = <&reg_audio_board>;
status = "disabled";
};
ak4458_2: ak4458@12 {
compatible = "asahi-kasei,ak4458";
reg = <0x12>;
AVDD-supply = <&reg_audio_board>;
DVDD-supply = <&reg_audio_board>;
status = "disabled";
};
ak5558: ak5558@13 {
compatible = "asahi-kasei,ak5558";
reg = <0x13>;
ak5558,pdn-gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
AVDD-supply = <&reg_audio_board>;
DVDD-supply = <&reg_audio_board>;
status = "disabled";
};
ak4497: ak4497@11 {
compatible = "asahi-kasei,ak4497";
reg = <0x11>;
ak4497,pdn-gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
AVDD-supply = <&reg_audio_board>;
DVDD-supply = <&reg_audio_board>;
status = "disabled";
};
ov5640_mipi_0: ov5640_mipi@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
clocks = <&clk IMX8MN_CLK_CLKO1>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
assigned-clock-rates = <24000000>;
csi_id = <0>;
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
mclk = <24000000>;
mclk_source = <0>;
mipi_csi;
status = "okay";
port {
ov5640_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
data-lanes = <1 2>;
clocks-lanes = <0>;
};
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt25qu256aba@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
rohm,reset-snvs-powered;
regulators {
buck1_reg: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck4_reg: BUCK4 {
// BUCK6 in datasheet
regulator-name = "BUCK4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
// BUCK7 in datasheet
regulator-name = "BUCK5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
// BUCK8 in datasheet
regulator-name = "BUCK6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "LDO6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
status = "okay";
port@1 {
dsim_to_adv7535: endpoint {
remote-endpoint = <&adv7535_from_dsim>;
attach-bridge;
};
};
};
&snvs_pwrkey {
status = "okay";
};
&uart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MN_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
resets = <&modem_reset>;
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
picophy,pre-emp-curr-control = <3>;
picophy,dc-vol-level-adjust = <7>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wlan>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wlan>;
bus-width = <4>;
pm-ignore-notify;
keep-power-in-suspend;
non-removable;
cap-power-off-card;
/delete-property/ vmmc-supply;
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&gpu {
assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
<&clk IMX8MN_CLK_GPU_SHADER_SRC>,
<&clk IMX8MN_CLK_GPU_AXI>,
<&clk IMX8MN_CLK_GPU_AHB>,
<&clk IMX8MN_GPU_PLL>,
<&clk IMX8MN_CLK_GPU_CORE_DIV>,
<&clk IMX8MN_CLK_GPU_SHADER_DIV>;
assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
<&clk IMX8MN_GPU_PLL_OUT>,
<&clk IMX8MN_SYS_PLL1_800M>,
<&clk IMX8MN_SYS_PLL1_800M>;
assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
<400000000>, <400000000>;
status= "okay";
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MN_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
assigned-clocks = <&clk IMX8MN_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <49152000>;
clocks = <&clk IMX8MN_CLK_SAI5_IPG>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_SAI5_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
<&clk IMX8MN_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-asynchronous;
status = "disabled";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_24M>,
<&clk IMX8MN_CLK_SPDIF1>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_AUDIO_PLL1_OUT>, <&clk IMX8MN_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
status = "okay";
};
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@0 {
reg = <0>;
mipi1_sensor_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
data-lanes = <2>;
csis-hs-settle = <13>;
csis-clk-settle = <2>;
csis-wclk;
};
};
};
&isi_0 {
status = "okay";
cap_device {
status = "okay";
};
};
&cameradev {
status = "okay";
};
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