184 lines
4.1 KiB
Plaintext
184 lines
4.1 KiB
Plaintext
/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 MicroSys Electronics GmbH
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* Copyright 2018-2019 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/dts-v1/;
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#include "s32v234.dtsi"
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/ {
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model = "Freescale S32V234";
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compatible = "fsl,s32v234-sbc", "fsl,s32v234";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&can0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0>;
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status = "okay";
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&siul2 {
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status = "okay";
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s32v234-sbc {
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/* Format of pins: MSCR_IDX PAD_CONFIGURATION If you know the
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* IMCR_IDX instead of MSCR_IDX, add 512 to it as the Reference
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* Manual states.
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*/
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pinctrl_can0: can0grp {
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fsl,pins = <
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S32V234_PAD_PA2__CAN_FD0_TXD
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S32V234_PAD_PA3__CAN_FD0_RXD_OUT
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S32V234_PAD_PA3__CAN_FD0_RXD_IN
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/*
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* Configure pin C12 as GPIO[6] in MSCR#6.
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* Effect: the S-pin at CAN is not longer
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* flowting at ~0.75V, but driven to low ~0.0V.
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*/
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S32V234_MSCR_PA6 (PAD_CTL_MUX_MODE_ALT0 \
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| PAD_CTL_OBE \
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| PAD_CTL_DSE_34 \
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| PAD_CTL_PUS_33K_UP)
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>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <
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S32V234_PAD_PA4__CAN_FD1_TXD
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S32V234_PAD_PA5__CAN_FD1_RXD_OUT
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S32V234_PAD_PA5__CAN_FD1_RXD_IN
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/*
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* Configure pin C11 as GPIO[7] in MSCR#7.
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* Effect: the S-pin at CAN is not longer
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* flowting at ~0.39V, but driven to low ~0.0V.
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*/
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S32V234_MSCR_PA7 (PAD_CTL_MUX_MODE_ALT0 \
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| PAD_CTL_OBE \
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| PAD_CTL_DSE_34 \
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| PAD_CTL_PUS_33K_UP)
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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S32V234_PAD_PC13__MDC
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S32V234_PAD_PC14__MDIO_OUT
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S32v234_PAD_PC14__MDIO_IN
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S32V234_PAD_PC15__TXCLK_OUT
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S32V234_PAD_PC15__TXCLK_IN
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S32V234_PAD_PD0__RXCLK_OUT
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S32V234_PAD_PD0__RXCLK_IN
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S32V234_PAD_PD1__RX_D0_OUT
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S32V234_PAD_PD1__RX_D0_IN
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S32V234_PAD_PD2__RX_D1_OUT
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S32V234_PAD_PD2__RX_D1_IN
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S32V234_PAD_PD3__RX_D2_OUT
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S32V234_PAD_PD3__RX_D2_IN
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S32V234_PAD_PD4__RX_D3_OUT
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S32V234_PAD_PD4__RX_D3_IN
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S32V234_PAD_PD4__RX_DV_OUT
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S32V234_PAD_PD4__RX_DV_IN
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S32V234_PAD_PD7__TX_D0_OUT
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S32V234_PAD_PD8__TX_D1_OUT
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S32V234_PAD_PD9__TX_D2_OUT
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S32V234_PAD_PD10__TX_D3_OUT
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S32V234_PAD_PD11__TX_EN_OUT
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>;
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};
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pinctrl_uart0: uart0grp {
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fsl,pins = <
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S32V234_PAD_PA12__UART0_TXD
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S32V234_PAD_PA11__UART0_RXD_OUT
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S32V234_PAD_PA11__UART0_RXD_IN
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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S32V234_PAD_PA14__UART1_TXD
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S32V234_PAD_PA13__UART1_RXD_OUT
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S32V234_PAD_PA13__UART1_RXD_IN
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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S32V234_PAD_PK6__USDHC_CLK_OUT
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S32V234_PAD_PK6__USDHC_CLK_IN
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S32V234_PAD_PK7__USDHC_CMD_OUT
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S32V234_PAD_PK7__USDHC_CMD_IN
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S32V234_PAD_PK8__USDHC_DAT0_OUT
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S32V234_PAD_PK8__USDHC_DAT0_IN
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S32V234_PAD_PK9__USDHC_DAT1_OUT
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S32V234_PAD_PK9__USDHC_DAT1_IN
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S32V234_PAD_PK10__USDHC_DAT2_OUT
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S32V234_PAD_PK10__USDHC_DAT2_IN
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S32V234_PAD_PK11__USDHC_DAT3_OUT
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S32V234_PAD_PK11__USDHC_DAT3_IN
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S32V234_PAD_PK15__USDHC_DAT4_OUT
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S32V234_PAD_PK15__USDHC_DAT4_IN
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S32V234_PAD_PL0__USDHC_DAT5_OUT
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S32V234_PAD_PL0__USDHC_DAT5_IN
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S32V234_PAD_PL1__USDHC_DAT6_OUT
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S32V234_PAD_PL1__USDHC_DAT6_IN
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S32V234_PAD_PL2__USDHC_DAT7_OUT
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S32V234_PAD_PL2__USDHC_DAT7_IN
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>;
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};
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc0 {
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no-1-8-v;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc0>;
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status = "okay";
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};
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