![Olof Johansson](/assets/img/avatar_default.png)
- mvebu - set aliases for ethernet interfaces - PCIe range for armada-xp-db - rm unused properties on A370 - kirkwood - assign sheevaplug pinmuxs to correct devices - enable second PCIe port for ts219 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.20 (GNU/Linux) iQEcBAABAgAGBQJRujTWAAoJEAi3KVZQDZAewwYH/iWl8JcRm0i0xyjYjj6v+XMk 2NauOq3A5yTWbI0H3oXi8QH0BBlUie30SuT85O675KS9no0tIbv8JlLx3PfhTjoB 3hrDKkhcD6jTqg7TgWL9w3Qdq2S0/XLgoZ4RDo35nrXsCodpkr5XaEPJP3ES1Zo+ n57cAgyw7edhohcIT/mKSv5WyOajbU4uWPxBr9i8sqZf9uTFOyOYQpWZMCvbJKc2 /MrQ0UfRhMgymcaYiO5oqihYn8C0HhxRBno1muXemR4Ovaxgdp040gPB0QnmGONo oibfWbOWnlx6KK8I/B231uCWuDEFm5q1sr/L/e17f1hi0S+R6fwREVgH/5Hf6MQ= =UXHW -----END PGP SIGNATURE----- Merge tag 'dt-3.11-5' of git://git.infradead.org/users/jcooper/linux into next/dt From Jason Cooper: mvebu dt changes for v3.11 (round 5) - mvebu - set aliases for ethernet interfaces - PCIe range for armada-xp-db - rm unused properties on A370 - kirkwood - assign sheevaplug pinmuxs to correct devices - enable second PCIe port for ts219 * tag 'dt-3.11-5' of git://git.infradead.org/users/jcooper/linux: ARM: Kirkwood: ts219: Enable second PCIe port in DT. ARM: mvebu: Remove device tree unused properties on A370 arm: mvebu: armada-xp-db: ensure PCIe range is specified arm: kirkwood: sheevaplug: move pinmux configs to the right devices ARM: mvebu: set aliases for ethernet controllers Signed-off-by: Olof Johansson <olof@lixom.net>
223 lines
5 KiB
Plaintext
223 lines
5 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 370 family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada 370 SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/include/ "skeleton.dtsi"
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/ {
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model = "Marvell Armada 370 family SoC";
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compatible = "marvell,armada370", "marvell,armada-370-xp";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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soc {
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ranges = <0 0xd0000000 0x0100000 /* internal registers */
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0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
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internal-regs {
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system-controller@18200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x100>;
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};
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L2: l2-cache {
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compatible = "marvell,aurora-outer-cache";
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reg = <0x08000 0x1000>;
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cache-id-part = <0x100>;
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wt-override;
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};
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interrupt-controller@20000 {
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reg = <0x20a00 0x1d0>, <0x21870 0x58>;
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};
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pinctrl {
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compatible = "marvell,mv88f6710-pinctrl";
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reg = <0x18000 0x38>;
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sdio_pins1: sdio-pins1 {
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marvell,pins = "mpp9", "mpp11", "mpp12",
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"mpp13", "mpp14", "mpp15";
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marvell,function = "sd0";
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};
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sdio_pins2: sdio-pins2 {
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marvell,pins = "mpp47", "mpp48", "mpp49",
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"mpp50", "mpp51", "mpp52";
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marvell,function = "sd0";
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};
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sdio_pins3: sdio-pins3 {
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marvell,pins = "mpp48", "mpp49", "mpp50",
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"mpp51", "mpp52", "mpp53";
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marvell,function = "sd0";
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};
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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gpio2: gpio@18180 {
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <91>;
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};
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coreclk: mvebu-sar@18230 {
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compatible = "marvell,armada-370-core-clock";
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reg = <0x18230 0x08>;
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#clock-cells = <1>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-370-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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xor@60800 {
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compatible = "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60A00 0x100>;
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status = "okay";
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xor00 {
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interrupts = <51>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <52>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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status = "okay";
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xor10 {
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interrupts = <94>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <95>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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usb@50000 {
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clocks = <&coreclk 0>;
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};
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usb@51000 {
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clocks = <&coreclk 0>;
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};
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thermal@18300 {
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compatible = "marvell,armada370-thermal";
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reg = <0x18300 0x4
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0x18304 0x4>;
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status = "okay";
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};
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 9>;
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status = "disabled";
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};
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};
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};
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};
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};
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