![Linus Torvalds](/assets/img/avatar_default.png)
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
1018 lines
26 KiB
C
1018 lines
26 KiB
C
/*
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* drivers/net/ether00.c
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*
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* Copyright (C) 2001 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* includes */
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#include <linux/config.h>
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#include <linux/pci.h>
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#include <linux/sched.h>
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#include <linux/netdevice.h>
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#include <linux/skbuff.h>
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#include <linux/etherdevice.h>
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#include <linux/module.h>
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#include <linux/tqueue.h>
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#include <linux/mtd/mtd.h>
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#include <linux/pld/pld_hotswap.h>
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#include <asm/arch/excalibur.h>
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#include <asm/arch/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include <asm/arch/ether00.h>
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#include <asm/arch/tdkphy.h>
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MODULE_AUTHOR("Clive Davies");
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MODULE_DESCRIPTION("Altera Ether00 IP core driver");
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MODULE_LICENSE("GPL");
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#define PKT_BUF_SZ 1540 /* Size of each rx buffer */
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#define ETH_NR 4 /* Number of MACs this driver supports */
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#define DEBUG(x)
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#define __dma_va(x) (unsigned int)((unsigned int)priv->dma_data+(((unsigned int)(x))&(EXC_SPSRAM_BLOCK0_SIZE-1)))
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#define __dma_pa(x) (unsigned int)(EXC_SPSRAM_BLOCK0_BASE+(((unsigned int)(x))-(unsigned int)priv->dma_data))
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#define ETHER00_BASE 0
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#define ETHER00_TYPE
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#define ETHER00_NAME "ether00"
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#define MAC_REG_SIZE 0x400 /* size of MAC register area */
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/* typedefs */
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/* The definition of the driver control structure */
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#define RX_NUM_BUFF 10
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#define RX_NUM_FDESC 10
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#define TX_NUM_FDESC 10
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struct tx_fda_ent{
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FDA_DESC fd;
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BUF_DESC bd;
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BUF_DESC pad;
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};
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struct rx_fda_ent{
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FDA_DESC fd;
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BUF_DESC bd;
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BUF_DESC pad;
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};
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struct rx_blist_ent{
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FDA_DESC fd;
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BUF_DESC bd;
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BUF_DESC pad;
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};
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struct net_priv
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{
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struct net_device_stats stats;
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struct sk_buff* skb;
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void* dma_data;
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struct rx_blist_ent* rx_blist_vp;
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struct rx_fda_ent* rx_fda_ptr;
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struct tx_fda_ent* tx_fdalist_vp;
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struct tq_struct tq_memupdate;
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unsigned char memupdate_scheduled;
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unsigned char rx_disabled;
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unsigned char queue_stopped;
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spinlock_t rx_lock;
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};
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static const char vendor_id[2]={0x07,0xed};
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#ifdef ETHER00_DEBUG
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/* Dump (most) registers for debugging puposes */
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static void dump_regs(struct net_device *dev){
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struct net_priv* priv=dev->priv;
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unsigned int* i;
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printk("\n RX free descriptor area:\n");
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for(i=(unsigned int*)priv->rx_fda_ptr;
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i<((unsigned int*)(priv->rx_fda_ptr+RX_NUM_FDESC));){
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printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
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i+=4;
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}
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printk("\n RX buffer list:\n");
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for(i=(unsigned int*)priv->rx_blist_vp;
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i<((unsigned int*)(priv->rx_blist_vp+RX_NUM_BUFF));){
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printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
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i+=4;
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}
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printk("\n TX frame descriptor list:\n");
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for(i=(unsigned int*)priv->tx_fdalist_vp;
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i<((unsigned int*)(priv->tx_fdalist_vp+TX_NUM_FDESC));){
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printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
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i+=4;
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}
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printk("\ndma ctl=%#x\n",readw(ETHER_DMA_CTL(dev->base_addr)));
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printk("txfrmptr=%#x\n",readw(ETHER_TXFRMPTR(dev->base_addr)));
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printk("txthrsh=%#x\n",readw(ETHER_TXTHRSH(dev->base_addr)));
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printk("txpollctr=%#x\n",readw(ETHER_TXPOLLCTR(dev->base_addr)));
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printk("blfrmptr=%#x\n",readw(ETHER_BLFRMPTR(dev->base_addr)));
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printk("rxfragsize=%#x\n",readw(ETHER_RXFRAGSIZE(dev->base_addr)));
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printk("tx_int_en=%#x\n",readw(ETHER_INT_EN(dev->base_addr)));
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printk("fda_bas=%#x\n",readw(ETHER_FDA_BAS(dev->base_addr)));
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printk("fda_lim=%#x\n",readw(ETHER_FDA_LIM(dev->base_addr)));
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printk("int_src=%#x\n",readw(ETHER_INT_SRC(dev->base_addr)));
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printk("pausecnt=%#x\n",readw(ETHER_PAUSECNT(dev->base_addr)));
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printk("rempaucnt=%#x\n",readw(ETHER_REMPAUCNT(dev->base_addr)));
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printk("txconfrmstat=%#x\n",readw(ETHER_TXCONFRMSTAT(dev->base_addr)));
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printk("mac_ctl=%#x\n",readw(ETHER_MAC_CTL(dev->base_addr)));
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printk("arc_ctl=%#x\n",readw(ETHER_ARC_CTL(dev->base_addr)));
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printk("tx_ctl=%#x\n",readw(ETHER_TX_CTL(dev->base_addr)));
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}
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#endif /* ETHER00_DEBUG */
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static int ether00_write_phy(struct net_device *dev, short address, short value)
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{
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volatile int count = 1024;
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writew(value,ETHER_MD_DATA(dev->base_addr));
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writew( ETHER_MD_CA_BUSY_MSK |
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ETHER_MD_CA_WR_MSK |
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(address & ETHER_MD_CA_ADDR_MSK),
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ETHER_MD_CA(dev->base_addr));
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/* Wait for the command to complete */
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while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
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count--;
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}
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if (!count){
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printk("Write to phy failed, addr=%#x, data=%#x\n",address, value);
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return -EIO;
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}
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return 0;
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}
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static int ether00_read_phy(struct net_device *dev, short address)
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{
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volatile int count = 1024;
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writew( ETHER_MD_CA_BUSY_MSK |
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(address & ETHER_MD_CA_ADDR_MSK),
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ETHER_MD_CA(dev->base_addr));
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/* Wait for the command to complete */
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while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
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count--;
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}
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if (!count){
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printk(KERN_WARNING "Read from phy timed out\n");
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return -EIO;
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}
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return readw(ETHER_MD_DATA(dev->base_addr));
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}
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static void ether00_phy_int(int irq_num, void* dev_id, struct pt_regs* regs)
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{
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struct net_device* dev=dev_id;
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int irq_status;
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irq_status=ether00_read_phy(dev, PHY_IRQ_CONTROL);
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if(irq_status & PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK){
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/*
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* Autonegotiation complete on epxa10db. The mac doesn't
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* twig if we're in full duplex so we need to check the
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* phy status register and configure the mac accordingly
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*/
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if(ether00_read_phy(dev, PHY_STATUS)&(PHY_STATUS_10T_F_MSK|PHY_STATUS_100_X_F_MSK)){
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int tmp;
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tmp=readl(ETHER_MAC_CTL(dev->base_addr));
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writel(tmp|ETHER_MAC_CTL_FULLDUP_MSK,ETHER_MAC_CTL(dev->base_addr));
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}
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}
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if(irq_status&PHY_IRQ_CONTROL_LS_CHG_INT_MSK){
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if(ether00_read_phy(dev, PHY_STATUS)& PHY_STATUS_LINK_MSK){
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/* Link is up */
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netif_carrier_on(dev);
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//printk("Carrier on\n");
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}else{
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netif_carrier_off(dev);
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//printk("Carrier off\n");
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}
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}
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}
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static void setup_blist_entry(struct sk_buff* skb,struct rx_blist_ent* blist_ent_ptr){
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/* Make the buffer consistent with the cache as the mac is going to write
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* directly into it*/
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blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
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blist_ent_ptr->bd.BuffData=(char*)__pa(skb->data);
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consistent_sync(skb->data,PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
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/* align IP on 16 Byte (DMA_CTL set to skip 2 bytes) */
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skb_reserve(skb,2);
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blist_ent_ptr->bd.BuffLength=PKT_BUF_SZ-2;
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blist_ent_ptr->fd.FDLength=1;
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blist_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
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blist_ent_ptr->bd.BDCtl=BDCTL_COWNSBD_MSK;
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}
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static int ether00_mem_init(struct net_device* dev)
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{
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struct net_priv* priv=dev->priv;
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struct tx_fda_ent *tx_fd_ptr,*tx_end_ptr;
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struct rx_blist_ent* blist_ent_ptr;
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int i;
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/*
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* Grab a block of on chip SRAM to contain the control stuctures for
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* the ethernet MAC. This uncached becuase it needs to be accesses by both
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* bus masters (cpu + mac). However, it shouldn't matter too much in terms
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* of speed as its on chip memory
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*/
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priv->dma_data=ioremap_nocache(EXC_SPSRAM_BLOCK0_BASE,EXC_SPSRAM_BLOCK0_SIZE );
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if (!priv->dma_data)
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return -ENOMEM;
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priv->rx_fda_ptr=(struct rx_fda_ent*)priv->dma_data;
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/*
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* Now share it out amongst the Frame descriptors and the buffer list
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*/
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priv->rx_blist_vp=(struct rx_blist_ent*)((unsigned int)priv->dma_data+RX_NUM_FDESC*sizeof(struct rx_fda_ent));
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/*
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*Initalise the FDA list
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*/
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/* set ownership to the controller */
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memset(priv->rx_fda_ptr,0x80,RX_NUM_FDESC*sizeof(struct rx_fda_ent));
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/*
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*Initialise the buffer list
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*/
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blist_ent_ptr=priv->rx_blist_vp;
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i=0;
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while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
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struct sk_buff *skb;
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blist_ent_ptr->fd.FDLength=1;
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skb=dev_alloc_skb(PKT_BUF_SZ);
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if(skb){
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setup_blist_entry(skb,blist_ent_ptr);
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blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(blist_ent_ptr+1);
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blist_ent_ptr->bd.BDStat=i++;
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blist_ent_ptr++;
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}
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else
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{
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printk("Failed to initalise buffer list\n");
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}
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}
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blist_ent_ptr--;
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blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->rx_blist_vp);
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priv->tx_fdalist_vp=(struct tx_fda_ent*)(priv->rx_blist_vp+RX_NUM_BUFF);
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/* Initialise the buffers to be a circular list. The mac will then go poll
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* the list until it finds a frame ready to transmit */
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tx_end_ptr=priv->tx_fdalist_vp+TX_NUM_FDESC;
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for(tx_fd_ptr=priv->tx_fdalist_vp;tx_fd_ptr<tx_end_ptr;tx_fd_ptr++){
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tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa((tx_fd_ptr+1));
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tx_fd_ptr->fd.FDCtl=1;
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tx_fd_ptr->fd.FDStat=0;
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tx_fd_ptr->fd.FDLength=1;
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}
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/* Change the last FDNext pointer to make a circular list */
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tx_fd_ptr--;
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tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->tx_fdalist_vp);
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/* Point the device at the chain of Rx and Tx Buffers */
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writel((unsigned int)__dma_pa(priv->rx_fda_ptr),ETHER_FDA_BAS(dev->base_addr));
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writel((RX_NUM_FDESC-1)*sizeof(struct rx_fda_ent),ETHER_FDA_LIM(dev->base_addr));
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writel((unsigned int)__dma_pa(priv->rx_blist_vp),ETHER_BLFRMPTR(dev->base_addr));
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writel((unsigned int)__dma_pa(priv->tx_fdalist_vp),ETHER_TXFRMPTR(dev->base_addr));
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return 0;
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}
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void ether00_mem_update(void* dev_id)
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{
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struct net_device* dev=dev_id;
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struct net_priv* priv=dev->priv;
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struct sk_buff* skb;
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struct tx_fda_ent *fda_ptr=priv->tx_fdalist_vp;
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struct rx_blist_ent* blist_ent_ptr;
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unsigned long flags;
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priv->tq_memupdate.sync=0;
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//priv->tq_memupdate.list=
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priv->memupdate_scheduled=0;
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/* Transmit interrupt */
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while(fda_ptr<(priv->tx_fdalist_vp+TX_NUM_FDESC)){
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if(!(FDCTL_COWNSFD_MSK&fda_ptr->fd.FDCtl) && (ETHER_TX_STAT_COMP_MSK&fda_ptr->fd.FDStat)){
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priv->stats.tx_packets++;
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priv->stats.tx_bytes+=fda_ptr->bd.BuffLength;
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skb=(struct sk_buff*)fda_ptr->fd.FDSystem;
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//printk("%d:txcln:fda=%#x skb=%#x\n",jiffies,fda_ptr,skb);
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dev_kfree_skb(skb);
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fda_ptr->fd.FDSystem=0;
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fda_ptr->fd.FDStat=0;
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fda_ptr->fd.FDCtl=0;
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}
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fda_ptr++;
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}
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/* Fill in any missing buffers from the received queue */
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spin_lock_irqsave(&priv->rx_lock,flags);
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blist_ent_ptr=priv->rx_blist_vp;
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while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
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/* fd.FDSystem of 0 indicates we failed to allocate the buffer in the ISR */
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if(!blist_ent_ptr->fd.FDSystem){
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struct sk_buff *skb;
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skb=dev_alloc_skb(PKT_BUF_SZ);
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blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
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if(skb){
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setup_blist_entry(skb,blist_ent_ptr);
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}
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else
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{
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break;
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}
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}
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blist_ent_ptr++;
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}
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spin_unlock_irqrestore(&priv->rx_lock,flags);
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if(priv->queue_stopped){
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//printk("%d:cln:start q\n",jiffies);
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netif_start_queue(dev);
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}
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if(priv->rx_disabled){
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//printk("%d:enable_irq\n",jiffies);
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priv->rx_disabled=0;
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writel(ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
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}
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}
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static void ether00_int( int irq_num, void* dev_id, struct pt_regs* regs)
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{
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struct net_device* dev=dev_id;
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struct net_priv* priv=dev->priv;
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unsigned int interruptValue;
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interruptValue=readl(ETHER_INT_SRC(dev->base_addr));
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//printk("INT_SRC=%x\n",interruptValue);
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if(!(readl(ETHER_INT_SRC(dev->base_addr)) & ETHER_INT_SRC_IRQ_MSK))
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{
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return; /* Interrupt wasn't caused by us!! */
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}
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if(readl(ETHER_INT_SRC(dev->base_addr))&
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(ETHER_INT_SRC_INTMACRX_MSK |
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ETHER_INT_SRC_FDAEX_MSK |
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ETHER_INT_SRC_BLEX_MSK)) {
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struct rx_blist_ent* blist_ent_ptr;
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struct rx_fda_ent* fda_ent_ptr;
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struct sk_buff* skb;
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fda_ent_ptr=priv->rx_fda_ptr;
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spin_lock(&priv->rx_lock);
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while(fda_ent_ptr<(priv->rx_fda_ptr+RX_NUM_FDESC)){
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int result;
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if(!(fda_ent_ptr->fd.FDCtl&FDCTL_COWNSFD_MSK))
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{
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/* This frame is ready for processing */
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/*find the corresponding buffer in the bufferlist */
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blist_ent_ptr=priv->rx_blist_vp+fda_ent_ptr->bd.BDStat;
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skb=(struct sk_buff*)blist_ent_ptr->fd.FDSystem;
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/* Pass this skb up the stack */
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skb->dev=dev;
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skb_put(skb,fda_ent_ptr->fd.FDLength);
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skb->protocol=eth_type_trans(skb,dev);
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skb->ip_summed=CHECKSUM_UNNECESSARY;
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result=netif_rx(skb);
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/* Update statistics */
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priv->stats.rx_packets++;
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priv->stats.rx_bytes+=fda_ent_ptr->fd.FDLength;
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/* Free the FDA entry */
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fda_ent_ptr->bd.BDStat=0xff;
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fda_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
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/* Allocate a new skb and point the bd entry to it */
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blist_ent_ptr->fd.FDSystem=0;
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skb=dev_alloc_skb(PKT_BUF_SZ);
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//printk("allocskb=%#x\n",skb);
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if(skb){
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setup_blist_entry(skb,blist_ent_ptr);
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}
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else if(!priv->memupdate_scheduled){
|
|
int tmp;
|
|
/* There are no buffers at the moment, so schedule */
|
|
/* the background task to sort this out */
|
|
schedule_task(&priv->tq_memupdate);
|
|
priv->memupdate_scheduled=1;
|
|
printk(KERN_DEBUG "%s:No buffers",dev->name);
|
|
/* If this interrupt was due to a lack of buffers then
|
|
* we'd better stop the receiver too */
|
|
if(interruptValueÐER_INT_SRC_BLEX_MSK){
|
|
priv->rx_disabled=1;
|
|
tmp=readl(ETHER_INT_SRC(dev->base_addr));
|
|
writel(tmp&~ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
|
|
printk(KERN_DEBUG "%s:Halting rx",dev->name);
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
fda_ent_ptr++;
|
|
}
|
|
spin_unlock(&priv->rx_lock);
|
|
|
|
/* Clear the interrupts */
|
|
writel(ETHER_INT_SRC_INTMACRX_MSK | ETHER_INT_SRC_FDAEX_MSK
|
|
| ETHER_INT_SRC_BLEX_MSK,ETHER_INT_SRC(dev->base_addr));
|
|
|
|
}
|
|
|
|
if(readl(ETHER_INT_SRC(dev->base_addr))ÐER_INT_SRC_INTMACTX_MSK){
|
|
|
|
if(!priv->memupdate_scheduled){
|
|
schedule_task(&priv->tq_memupdate);
|
|
priv->memupdate_scheduled=1;
|
|
}
|
|
/* Clear the interrupt */
|
|
writel(ETHER_INT_SRC_INTMACTX_MSK,ETHER_INT_SRC(dev->base_addr));
|
|
}
|
|
|
|
if (readl(ETHER_INT_SRC(dev->base_addr)) & (ETHER_INT_SRC_SWINT_MSK|
|
|
ETHER_INT_SRC_INTEARNOT_MSK|
|
|
ETHER_INT_SRC_INTLINK_MSK|
|
|
ETHER_INT_SRC_INTEXBD_MSK|
|
|
ETHER_INT_SRC_INTTXCTLCMP_MSK))
|
|
{
|
|
/*
|
|
* Not using any of these so they shouldn't happen
|
|
*
|
|
* In the cased of INTEXBD - if you allocate more
|
|
* than 28 decsriptors you may need to think about this
|
|
*/
|
|
printk("Not using this interrupt\n");
|
|
}
|
|
|
|
if (readl(ETHER_INT_SRC(dev->base_addr)) &
|
|
(ETHER_INT_SRC_INTSBUS_MSK |
|
|
ETHER_INT_SRC_INTNRABT_MSK
|
|
|ETHER_INT_SRC_DMPARERR_MSK))
|
|
{
|
|
/*
|
|
* Hardware errors, we can either ignore them and hope they go away
|
|
*or reset the device, I'll try the first for now to see if they happen
|
|
*/
|
|
printk("Hardware error\n");
|
|
}
|
|
}
|
|
|
|
static void ether00_setup_ethernet_address(struct net_device* dev)
|
|
{
|
|
int tmp;
|
|
|
|
dev->addr_len=6;
|
|
writew(0,ETHER_ARC_ADR(dev->base_addr));
|
|
writel((dev->dev_addr[0]<<24) |
|
|
(dev->dev_addr[1]<<16) |
|
|
(dev->dev_addr[2]<<8) |
|
|
dev->dev_addr[3],
|
|
ETHER_ARC_DATA(dev->base_addr));
|
|
|
|
writew(4,ETHER_ARC_ADR(dev->base_addr));
|
|
tmp=readl(ETHER_ARC_DATA(dev->base_addr));
|
|
tmp&=0xffff;
|
|
tmp|=(dev->dev_addr[4]<<24) | (dev->dev_addr[5]<<16);
|
|
writel(tmp, ETHER_ARC_DATA(dev->base_addr));
|
|
/* Enable this entry in the ARC */
|
|
|
|
writel(1,ETHER_ARC_ENA(dev->base_addr));
|
|
|
|
return;
|
|
}
|
|
|
|
|
|
static void ether00_reset(struct net_device *dev)
|
|
{
|
|
/* reset the controller */
|
|
writew(ETHER_MAC_CTL_RESET_MSK,ETHER_MAC_CTL(dev->base_addr));
|
|
|
|
/*
|
|
* Make sure we're not going to send anything
|
|
*/
|
|
|
|
writew(ETHER_TX_CTL_TXHALT_MSK,ETHER_TX_CTL(dev->base_addr));
|
|
|
|
/*
|
|
* Make sure we're not going to receive anything
|
|
*/
|
|
writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
|
|
|
|
/*
|
|
* Disable Interrupts for now, and set the burst size to 8 bytes
|
|
*/
|
|
|
|
writel(ETHER_DMA_CTL_INTMASK_MSK |
|
|
((8 << ETHER_DMA_CTL_DMBURST_OFST) & ETHER_DMA_CTL_DMBURST_MSK)
|
|
|(2<<ETHER_DMA_CTL_RXALIGN_OFST),
|
|
ETHER_DMA_CTL(dev->base_addr));
|
|
|
|
|
|
/*
|
|
* Set TxThrsh - start transmitting a packet after 1514
|
|
* bytes or when a packet is complete, whichever comes first
|
|
*/
|
|
writew(1514,ETHER_TXTHRSH(dev->base_addr));
|
|
|
|
/*
|
|
* Set TxPollCtr. Each cycle is
|
|
* 61.44 microseconds with a 33 MHz bus
|
|
*/
|
|
writew(1,ETHER_TXPOLLCTR(dev->base_addr));
|
|
|
|
/*
|
|
* Set Rx_Ctl - Turn off reception and let RxData turn it
|
|
* on later
|
|
*/
|
|
writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
|
|
|
|
}
|
|
|
|
|
|
static void ether00_set_multicast(struct net_device* dev)
|
|
{
|
|
int count=dev->mc_count;
|
|
|
|
/* Set promiscuous mode if it's asked for. */
|
|
|
|
if (dev->flags&IFF_PROMISC){
|
|
|
|
writew( ETHER_ARC_CTL_COMPEN_MSK |
|
|
ETHER_ARC_CTL_BROADACC_MSK |
|
|
ETHER_ARC_CTL_GROUPACC_MSK |
|
|
ETHER_ARC_CTL_STATIONACC_MSK,
|
|
ETHER_ARC_CTL(dev->base_addr));
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Get all multicast packets if required, or if there are too
|
|
* many addresses to fit in hardware
|
|
*/
|
|
if (dev->flags & IFF_ALLMULTI){
|
|
writew( ETHER_ARC_CTL_COMPEN_MSK |
|
|
ETHER_ARC_CTL_GROUPACC_MSK |
|
|
ETHER_ARC_CTL_BROADACC_MSK,
|
|
ETHER_ARC_CTL(dev->base_addr));
|
|
return;
|
|
}
|
|
if (dev->mc_count > (ETHER_ARC_SIZE - 1)){
|
|
|
|
printk(KERN_WARNING "Too many multicast addresses for hardware to filter - receiving all multicast packets\n");
|
|
writew( ETHER_ARC_CTL_COMPEN_MSK |
|
|
ETHER_ARC_CTL_GROUPACC_MSK |
|
|
ETHER_ARC_CTL_BROADACC_MSK,
|
|
ETHER_ARC_CTL(dev->base_addr));
|
|
return;
|
|
}
|
|
|
|
if(dev->mc_count){
|
|
struct dev_mc_list *mc_list_ent=dev->mc_list;
|
|
unsigned int temp,i;
|
|
DEBUG(printk("mc_count=%d mc_list=%#x\n",dev-> mc_count, dev->mc_list));
|
|
DEBUG(printk("mc addr=%02#x%02x%02x%02x%02x%02x\n",
|
|
mc_list_ent->dmi_addr[5],
|
|
mc_list_ent->dmi_addr[4],
|
|
mc_list_ent->dmi_addr[3],
|
|
mc_list_ent->dmi_addr[2],
|
|
mc_list_ent->dmi_addr[1],
|
|
mc_list_ent->dmi_addr[0]);)
|
|
|
|
/*
|
|
* The first 6 bytes are the MAC address, so
|
|
* don't change them!
|
|
*/
|
|
writew(4,ETHER_ARC_ADR(dev->base_addr));
|
|
temp=readl(ETHER_ARC_DATA(dev->base_addr));
|
|
temp&=0xffff0000;
|
|
|
|
/* Disable the current multicast stuff */
|
|
writel(1,ETHER_ARC_ENA(dev->base_addr));
|
|
|
|
for(;;){
|
|
temp|=mc_list_ent->dmi_addr[1] |
|
|
mc_list_ent->dmi_addr[0]<<8;
|
|
writel(temp,ETHER_ARC_DATA(dev->base_addr));
|
|
|
|
i=readl(ETHER_ARC_ADR(dev->base_addr));
|
|
writew(i+4,ETHER_ARC_ADR(dev->base_addr));
|
|
|
|
temp=mc_list_ent->dmi_addr[5]|
|
|
mc_list_ent->dmi_addr[4]<<8 |
|
|
mc_list_ent->dmi_addr[3]<<16 |
|
|
mc_list_ent->dmi_addr[2]<<24;
|
|
writel(temp,ETHER_ARC_DATA(dev->base_addr));
|
|
|
|
count--;
|
|
if(!mc_list_ent->next || !count){
|
|
break;
|
|
}
|
|
DEBUG(printk("mc_list_next=%#x\n",mc_list_ent->next);)
|
|
mc_list_ent=mc_list_ent->next;
|
|
|
|
|
|
i=readl(ETHER_ARC_ADR(dev->base_addr));
|
|
writel(i+4,ETHER_ARC_ADR(dev->base_addr));
|
|
|
|
temp=mc_list_ent->dmi_addr[3]|
|
|
mc_list_ent->dmi_addr[2]<<8 |
|
|
mc_list_ent->dmi_addr[1]<<16 |
|
|
mc_list_ent->dmi_addr[0]<<24;
|
|
writel(temp,ETHER_ARC_DATA(dev->base_addr));
|
|
|
|
i=readl(ETHER_ARC_ADR(dev->base_addr));
|
|
writel(i+4,ETHER_ARC_ADR(dev->base_addr));
|
|
|
|
temp=mc_list_ent->dmi_addr[4]<<16 |
|
|
mc_list_ent->dmi_addr[5]<<24;
|
|
|
|
writel(temp,ETHER_ARC_DATA(dev->base_addr));
|
|
|
|
count--;
|
|
if(!mc_list_ent->next || !count){
|
|
break;
|
|
}
|
|
mc_list_ent=mc_list_ent->next;
|
|
}
|
|
|
|
|
|
if(count)
|
|
printk(KERN_WARNING "Multicast list size error\n");
|
|
|
|
|
|
writew( ETHER_ARC_CTL_BROADACC_MSK|
|
|
ETHER_ARC_CTL_COMPEN_MSK,
|
|
ETHER_ARC_CTL(dev->base_addr));
|
|
|
|
}
|
|
|
|
/* enable the active ARC enties */
|
|
writew((1<<(count+2))-1,ETHER_ARC_ENA(dev->base_addr));
|
|
}
|
|
|
|
|
|
static int ether00_open(struct net_device* dev)
|
|
{
|
|
int result,tmp;
|
|
struct net_priv* priv;
|
|
|
|
if (!is_valid_ether_addr(dev->dev_addr))
|
|
return -EINVAL;
|
|
|
|
/* Install interrupt handlers */
|
|
result=request_irq(dev->irq,ether00_int,0,"ether00",dev);
|
|
if(result)
|
|
goto open_err1;
|
|
|
|
result=request_irq(2,ether00_phy_int,0,"ether00_phy",dev);
|
|
if(result)
|
|
goto open_err2;
|
|
|
|
ether00_reset(dev);
|
|
result=ether00_mem_init(dev);
|
|
if(result)
|
|
goto open_err3;
|
|
|
|
|
|
ether00_setup_ethernet_address(dev);
|
|
|
|
ether00_set_multicast(dev);
|
|
|
|
result=ether00_write_phy(dev,PHY_CONTROL, PHY_CONTROL_ANEGEN_MSK | PHY_CONTROL_RANEG_MSK);
|
|
if(result)
|
|
goto open_err4;
|
|
result=ether00_write_phy(dev,PHY_IRQ_CONTROL, PHY_IRQ_CONTROL_LS_CHG_IE_MSK |
|
|
PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK);
|
|
if(result)
|
|
goto open_err4;
|
|
|
|
/* Start the device enable interrupts */
|
|
writew(ETHER_RX_CTL_RXEN_MSK
|
|
// | ETHER_RX_CTL_STRIPCRC_MSK
|
|
| ETHER_RX_CTL_ENGOOD_MSK
|
|
| ETHER_RX_CTL_ENRXPAR_MSK| ETHER_RX_CTL_ENLONGERR_MSK
|
|
| ETHER_RX_CTL_ENOVER_MSK| ETHER_RX_CTL_ENCRCERR_MSK,
|
|
ETHER_RX_CTL(dev->base_addr));
|
|
|
|
writew(ETHER_TX_CTL_TXEN_MSK|
|
|
ETHER_TX_CTL_ENEXDEFER_MSK|
|
|
ETHER_TX_CTL_ENLCARR_MSK|
|
|
ETHER_TX_CTL_ENEXCOLL_MSK|
|
|
ETHER_TX_CTL_ENLATECOLL_MSK|
|
|
ETHER_TX_CTL_ENTXPAR_MSK|
|
|
ETHER_TX_CTL_ENCOMP_MSK,
|
|
ETHER_TX_CTL(dev->base_addr));
|
|
|
|
tmp=readl(ETHER_DMA_CTL(dev->base_addr));
|
|
writel(tmp&~ETHER_DMA_CTL_INTMASK_MSK,ETHER_DMA_CTL(dev->base_addr));
|
|
|
|
return 0;
|
|
|
|
open_err4:
|
|
ether00_reset(dev);
|
|
open_err3:
|
|
free_irq(2,dev);
|
|
open_err2:
|
|
free_irq(dev->irq,dev);
|
|
open_err1:
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
static int ether00_tx(struct sk_buff* skb, struct net_device* dev)
|
|
{
|
|
struct net_priv *priv=dev->priv;
|
|
struct tx_fda_ent *fda_ptr;
|
|
int i;
|
|
|
|
|
|
/*
|
|
* Find an empty slot in which to stick the frame
|
|
*/
|
|
fda_ptr=(struct tx_fda_ent*)__dma_va(readl(ETHER_TXFRMPTR(dev->base_addr)));
|
|
i=0;
|
|
while(i<TX_NUM_FDESC){
|
|
if (fda_ptr->fd.FDStat||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
|
|
fda_ptr =(struct tx_fda_ent*) __dma_va((struct tx_fda_ent*)fda_ptr->fd.FDNext);
|
|
}
|
|
else {
|
|
break;
|
|
}
|
|
i++;
|
|
}
|
|
|
|
/* Write the skb data from the cache*/
|
|
consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
|
|
fda_ptr->bd.BuffData=(char*)__pa(skb->data);
|
|
fda_ptr->bd.BuffLength=(unsigned short)skb->len;
|
|
/* Save the pointer to the skb for freeing later */
|
|
fda_ptr->fd.FDSystem=(unsigned int)skb;
|
|
fda_ptr->fd.FDStat=0;
|
|
/* Pass ownership of the buffers to the controller */
|
|
fda_ptr->fd.FDCtl=1;
|
|
fda_ptr->fd.FDCtl|=FDCTL_COWNSFD_MSK;
|
|
|
|
/* If the next buffer in the list is full, stop the queue */
|
|
fda_ptr=(struct tx_fda_ent*)__dma_va(fda_ptr->fd.FDNext);
|
|
if ((fda_ptr->fd.FDStat)||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
|
|
netif_stop_queue(dev);
|
|
priv->queue_stopped=1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct net_device_stats *ether00_stats(struct net_device* dev)
|
|
{
|
|
struct net_priv *priv=dev->priv;
|
|
return &priv->stats;
|
|
}
|
|
|
|
|
|
static int ether00_stop(struct net_device* dev)
|
|
{
|
|
struct net_priv *priv=dev->priv;
|
|
int tmp;
|
|
|
|
/* Stop/disable the device. */
|
|
tmp=readw(ETHER_RX_CTL(dev->base_addr));
|
|
tmp&=~(ETHER_RX_CTL_RXEN_MSK | ETHER_RX_CTL_ENGOOD_MSK);
|
|
tmp|=ETHER_RX_CTL_RXHALT_MSK;
|
|
writew(tmp,ETHER_RX_CTL(dev->base_addr));
|
|
|
|
tmp=readl(ETHER_TX_CTL(dev->base_addr));
|
|
tmp&=~ETHER_TX_CTL_TXEN_MSK;
|
|
tmp|=ETHER_TX_CTL_TXHALT_MSK;
|
|
writel(tmp,ETHER_TX_CTL(dev->base_addr));
|
|
|
|
/* Free up system resources */
|
|
free_irq(dev->irq,dev);
|
|
free_irq(2,dev);
|
|
iounmap(priv->dma_data);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static void ether00_get_ethernet_address(struct net_device* dev)
|
|
{
|
|
struct mtd_info *mymtd=NULL;
|
|
int i;
|
|
size_t retlen;
|
|
|
|
/*
|
|
* For the Epxa10 dev board (camelot), the ethernet MAC
|
|
* address is of the form 00:aa:aa:00:xx:xx where
|
|
* 00:aa:aa is the Altera vendor ID and xx:xx is the
|
|
* last 2 bytes of the board serial number, as programmed
|
|
* into the OTP area of the flash device on EBI1. If this
|
|
* isn't an expa10 dev board, or there's no mtd support to
|
|
* read the serial number from flash then we'll force the
|
|
* use to set their own mac address using ifconfig.
|
|
*/
|
|
|
|
#ifdef CONFIG_ARCH_CAMELOT
|
|
#ifdef CONFIG_MTD
|
|
/* get the mtd_info structure for the first mtd device*/
|
|
for(i=0;i<MAX_MTD_DEVICES;i++){
|
|
mymtd=get_mtd_device(NULL,i);
|
|
if(!mymtd||!strcmp(mymtd->name,"EPXA10DB flash"))
|
|
break;
|
|
}
|
|
|
|
if(!mymtd || !mymtd->read_user_prot_reg){
|
|
printk(KERN_WARNING "%s: Failed to read MAC address from flash\n",dev->name);
|
|
}else{
|
|
mymtd->read_user_prot_reg(mymtd,2,1,&retlen,&dev->dev_addr[5]);
|
|
mymtd->read_user_prot_reg(mymtd,3,1,&retlen,&dev->dev_addr[4]);
|
|
dev->dev_addr[3]=0;
|
|
dev->dev_addr[2]=vendor_id[1];
|
|
dev->dev_addr[1]=vendor_id[0];
|
|
dev->dev_addr[0]=0;
|
|
}
|
|
#else
|
|
printk(KERN_WARNING "%s: MTD support required to read MAC address from EPXA10 dev board\n", dev->name);
|
|
#endif
|
|
#endif
|
|
|
|
if (!is_valid_ether_addr(dev->dev_addr))
|
|
printk("%s: Invalid ethernet MAC address. Please set using "
|
|
"ifconfig\n", dev->name);
|
|
|
|
}
|
|
|
|
/*
|
|
* Keep a mapping of dev_info addresses -> port lines to use when
|
|
* removing ports dev==NULL indicates unused entry
|
|
*/
|
|
|
|
|
|
static struct net_device* dev_list[ETH_NR];
|
|
|
|
static int ether00_add_device(struct pldhs_dev_info* dev_info,void* dev_ps_data)
|
|
{
|
|
struct net_device *dev;
|
|
struct net_priv *priv;
|
|
void *map_addr;
|
|
int result;
|
|
int i;
|
|
|
|
i=0;
|
|
while(dev_list[i] && i < ETH_NR)
|
|
i++;
|
|
|
|
if(i==ETH_NR){
|
|
printk(KERN_WARNING "ether00: Maximum number of ports reached\n");
|
|
return 0;
|
|
}
|
|
|
|
|
|
if (!request_mem_region(dev_info->base_addr, MAC_REG_SIZE, "ether00"))
|
|
return -EBUSY;
|
|
|
|
dev = alloc_etherdev(sizeof(struct net_priv));
|
|
if(!dev) {
|
|
result = -ENOMEM;
|
|
goto out_release;
|
|
}
|
|
priv = dev->priv;
|
|
|
|
priv->tq_memupdate.routine=ether00_mem_update;
|
|
priv->tq_memupdate.data=(void*) dev;
|
|
|
|
spin_lock_init(&priv->rx_lock);
|
|
|
|
map_addr=ioremap_nocache(dev_info->base_addr,SZ_4K);
|
|
if(!map_addr){
|
|
result = -ENOMEM;
|
|
out_kfree;
|
|
}
|
|
|
|
dev->open=ether00_open;
|
|
dev->stop=ether00_stop;
|
|
dev->set_multicast_list=ether00_set_multicast;
|
|
dev->hard_start_xmit=ether00_tx;
|
|
dev->get_stats=ether00_stats;
|
|
|
|
ether00_get_ethernet_address(dev);
|
|
|
|
SET_MODULE_OWNER(dev);
|
|
|
|
dev->base_addr=(unsigned int)map_addr;
|
|
dev->irq=dev_info->irq;
|
|
dev->features=NETIF_F_DYNALLOC | NETIF_F_HW_CSUM;
|
|
|
|
result=register_netdev(dev);
|
|
if(result){
|
|
printk("Ether00: Error %i registering driver\n",result);
|
|
goto out_unmap;
|
|
}
|
|
printk("registered ether00 device at %#x\n",dev_info->base_addr);
|
|
|
|
dev_list[i]=dev;
|
|
|
|
return result;
|
|
|
|
out_unmap:
|
|
iounmap(map_addr);
|
|
out_kfree:
|
|
free_netdev(dev);
|
|
out_release:
|
|
release_mem_region(dev_info->base_addr, MAC_REG_SIZE);
|
|
return result;
|
|
}
|
|
|
|
|
|
static int ether00_remove_devices(void)
|
|
{
|
|
int i;
|
|
|
|
for(i=0;i<ETH_NR;i++){
|
|
if(dev_list[i]){
|
|
netif_device_detach(dev_list[i]);
|
|
unregister_netdev(dev_list[i]);
|
|
iounmap((void*)dev_list[i]->base_addr);
|
|
release_mem_region(dev_list[i]->base_addr, MAC_REG_SIZE);
|
|
free_netdev(dev_list[i]);
|
|
dev_list[i]=0;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct pld_hotswap_ops ether00_pldhs_ops={
|
|
.name = ETHER00_NAME,
|
|
.add_device = ether00_add_device,
|
|
.remove_devices = ether00_remove_devices,
|
|
};
|
|
|
|
|
|
static void __exit ether00_cleanup_module(void)
|
|
{
|
|
int result;
|
|
result=ether00_remove_devices();
|
|
if(result)
|
|
printk(KERN_WARNING "ether00: failed to remove all devices\n");
|
|
|
|
pldhs_unregister_driver(ETHER00_NAME);
|
|
}
|
|
module_exit(ether00_cleanup_module);
|
|
|
|
|
|
static int __init ether00_mod_init(void)
|
|
{
|
|
printk("mod init\n");
|
|
return pldhs_register_driver(ðer00_pldhs_ops);
|
|
|
|
}
|
|
|
|
module_init(ether00_mod_init);
|
|
|