![Borislav Petkov](/assets/img/avatar_default.png)
We use sync_core() in the alternatives code to stop speculative execution of prefetched instructions because we are potentially changing them and don't want to execute stale bytes. What it does on most machines is call CPUID which is a serializing instruction. And that's expensive. However, the instruction cache is serialized when we're on the local CPU and are changing the data through the same virtual address. So then, we don't need the serializing CPUID but a simple control flow change. Last being accomplished with a CALL/RET which the noinline causes. Suggested-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: Andy Lutomirski <luto@kernel.org> Cc: Andrew Cooper <andrew.cooper3@citrix.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Brian Gerst <brgerst@gmail.com> Cc: Henrique de Moraes Holschuh <hmh@hmh.eng.br> Cc: Matthew Whitehead <tedheadster@gmail.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20161203150258.vwr5zzco7ctgc4pe@pd.tnic Signed-off-by: Ingo Molnar <mingo@kernel.org>
820 lines
20 KiB
C
820 lines
20 KiB
C
#define pr_fmt(fmt) "SMP alternatives: " fmt
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/stringify.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/memory.h>
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#include <linux/stop_machine.h>
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#include <linux/slab.h>
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#include <linux/kdebug.h>
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#include <asm/text-patching.h>
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#include <asm/alternative.h>
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#include <asm/sections.h>
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#include <asm/pgtable.h>
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#include <asm/mce.h>
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#include <asm/nmi.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/io.h>
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#include <asm/fixmap.h>
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int __read_mostly alternatives_patched;
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EXPORT_SYMBOL_GPL(alternatives_patched);
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#define MAX_PATCH_LEN (255-1)
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static int __initdata_or_module debug_alternative;
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static int __init debug_alt(char *str)
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{
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debug_alternative = 1;
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return 1;
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}
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__setup("debug-alternative", debug_alt);
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static int noreplace_smp;
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static int __init setup_noreplace_smp(char *str)
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{
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noreplace_smp = 1;
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return 1;
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}
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__setup("noreplace-smp", setup_noreplace_smp);
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#ifdef CONFIG_PARAVIRT
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static int __initdata_or_module noreplace_paravirt = 0;
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static int __init setup_noreplace_paravirt(char *str)
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{
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noreplace_paravirt = 1;
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return 1;
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}
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__setup("noreplace-paravirt", setup_noreplace_paravirt);
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#endif
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#define DPRINTK(fmt, args...) \
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do { \
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if (debug_alternative) \
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printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
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} while (0)
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#define DUMP_BYTES(buf, len, fmt, args...) \
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do { \
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if (unlikely(debug_alternative)) { \
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int j; \
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\
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if (!(len)) \
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break; \
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\
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printk(KERN_DEBUG fmt, ##args); \
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for (j = 0; j < (len) - 1; j++) \
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printk(KERN_CONT "%02hhx ", buf[j]); \
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printk(KERN_CONT "%02hhx\n", buf[j]); \
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} \
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} while (0)
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/*
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* Each GENERIC_NOPX is of X bytes, and defined as an array of bytes
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* that correspond to that nop. Getting from one nop to the next, we
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* add to the array the offset that is equal to the sum of all sizes of
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* nops preceding the one we are after.
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*
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* Note: The GENERIC_NOP5_ATOMIC is at the end, as it breaks the
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* nice symmetry of sizes of the previous nops.
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*/
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#if defined(GENERIC_NOP1) && !defined(CONFIG_X86_64)
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static const unsigned char intelnops[] =
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{
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GENERIC_NOP1,
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GENERIC_NOP2,
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GENERIC_NOP3,
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GENERIC_NOP4,
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GENERIC_NOP5,
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GENERIC_NOP6,
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GENERIC_NOP7,
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GENERIC_NOP8,
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GENERIC_NOP5_ATOMIC
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};
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static const unsigned char * const intel_nops[ASM_NOP_MAX+2] =
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{
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NULL,
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intelnops,
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intelnops + 1,
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intelnops + 1 + 2,
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intelnops + 1 + 2 + 3,
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intelnops + 1 + 2 + 3 + 4,
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intelnops + 1 + 2 + 3 + 4 + 5,
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intelnops + 1 + 2 + 3 + 4 + 5 + 6,
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intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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};
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#endif
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#ifdef K8_NOP1
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static const unsigned char k8nops[] =
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{
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K8_NOP1,
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K8_NOP2,
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K8_NOP3,
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K8_NOP4,
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K8_NOP5,
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K8_NOP6,
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K8_NOP7,
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K8_NOP8,
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K8_NOP5_ATOMIC
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};
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static const unsigned char * const k8_nops[ASM_NOP_MAX+2] =
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{
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NULL,
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k8nops,
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k8nops + 1,
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k8nops + 1 + 2,
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k8nops + 1 + 2 + 3,
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k8nops + 1 + 2 + 3 + 4,
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k8nops + 1 + 2 + 3 + 4 + 5,
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k8nops + 1 + 2 + 3 + 4 + 5 + 6,
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k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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};
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#endif
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#if defined(K7_NOP1) && !defined(CONFIG_X86_64)
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static const unsigned char k7nops[] =
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{
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K7_NOP1,
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K7_NOP2,
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K7_NOP3,
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K7_NOP4,
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K7_NOP5,
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K7_NOP6,
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K7_NOP7,
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K7_NOP8,
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K7_NOP5_ATOMIC
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};
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static const unsigned char * const k7_nops[ASM_NOP_MAX+2] =
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{
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NULL,
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k7nops,
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k7nops + 1,
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k7nops + 1 + 2,
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k7nops + 1 + 2 + 3,
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k7nops + 1 + 2 + 3 + 4,
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k7nops + 1 + 2 + 3 + 4 + 5,
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k7nops + 1 + 2 + 3 + 4 + 5 + 6,
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k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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};
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#endif
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#ifdef P6_NOP1
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static const unsigned char p6nops[] =
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{
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P6_NOP1,
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P6_NOP2,
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P6_NOP3,
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P6_NOP4,
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P6_NOP5,
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P6_NOP6,
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P6_NOP7,
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P6_NOP8,
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P6_NOP5_ATOMIC
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};
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static const unsigned char * const p6_nops[ASM_NOP_MAX+2] =
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{
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NULL,
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p6nops,
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p6nops + 1,
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p6nops + 1 + 2,
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p6nops + 1 + 2 + 3,
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p6nops + 1 + 2 + 3 + 4,
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p6nops + 1 + 2 + 3 + 4 + 5,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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};
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#endif
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/* Initialize these to a safe default */
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#ifdef CONFIG_X86_64
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const unsigned char * const *ideal_nops = p6_nops;
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#else
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const unsigned char * const *ideal_nops = intel_nops;
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#endif
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void __init arch_init_ideal_nops(void)
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{
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
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/*
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* Due to a decoder implementation quirk, some
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* specific Intel CPUs actually perform better with
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* the "k8_nops" than with the SDM-recommended NOPs.
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*/
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if (boot_cpu_data.x86 == 6 &&
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boot_cpu_data.x86_model >= 0x0f &&
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boot_cpu_data.x86_model != 0x1c &&
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boot_cpu_data.x86_model != 0x26 &&
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boot_cpu_data.x86_model != 0x27 &&
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boot_cpu_data.x86_model < 0x30) {
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ideal_nops = k8_nops;
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} else if (boot_cpu_has(X86_FEATURE_NOPL)) {
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ideal_nops = p6_nops;
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} else {
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#ifdef CONFIG_X86_64
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ideal_nops = k8_nops;
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#else
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ideal_nops = intel_nops;
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#endif
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}
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break;
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case X86_VENDOR_AMD:
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if (boot_cpu_data.x86 > 0xf) {
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ideal_nops = p6_nops;
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return;
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}
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/* fall through */
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default:
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#ifdef CONFIG_X86_64
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ideal_nops = k8_nops;
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#else
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if (boot_cpu_has(X86_FEATURE_K8))
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ideal_nops = k8_nops;
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else if (boot_cpu_has(X86_FEATURE_K7))
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ideal_nops = k7_nops;
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else
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ideal_nops = intel_nops;
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#endif
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}
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}
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/* Use this to add nops to a buffer, then text_poke the whole buffer. */
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static void __init_or_module add_nops(void *insns, unsigned int len)
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{
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while (len > 0) {
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unsigned int noplen = len;
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if (noplen > ASM_NOP_MAX)
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noplen = ASM_NOP_MAX;
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memcpy(insns, ideal_nops[noplen], noplen);
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insns += noplen;
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len -= noplen;
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}
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}
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extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
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extern s32 __smp_locks[], __smp_locks_end[];
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void *text_poke_early(void *addr, const void *opcode, size_t len);
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/*
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* Are we looking at a near JMP with a 1 or 4-byte displacement.
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*/
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static inline bool is_jmp(const u8 opcode)
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{
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return opcode == 0xeb || opcode == 0xe9;
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}
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static void __init_or_module
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recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insnbuf)
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{
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u8 *next_rip, *tgt_rip;
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s32 n_dspl, o_dspl;
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int repl_len;
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if (a->replacementlen != 5)
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return;
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o_dspl = *(s32 *)(insnbuf + 1);
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/* next_rip of the replacement JMP */
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next_rip = repl_insn + a->replacementlen;
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/* target rip of the replacement JMP */
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tgt_rip = next_rip + o_dspl;
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n_dspl = tgt_rip - orig_insn;
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DPRINTK("target RIP: %p, new_displ: 0x%x", tgt_rip, n_dspl);
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if (tgt_rip - orig_insn >= 0) {
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if (n_dspl - 2 <= 127)
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goto two_byte_jmp;
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else
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goto five_byte_jmp;
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/* negative offset */
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} else {
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if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
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goto two_byte_jmp;
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else
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goto five_byte_jmp;
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}
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two_byte_jmp:
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n_dspl -= 2;
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insnbuf[0] = 0xeb;
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insnbuf[1] = (s8)n_dspl;
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add_nops(insnbuf + 2, 3);
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repl_len = 2;
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goto done;
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five_byte_jmp:
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n_dspl -= 5;
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insnbuf[0] = 0xe9;
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*(s32 *)&insnbuf[1] = n_dspl;
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repl_len = 5;
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done:
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DPRINTK("final displ: 0x%08x, JMP 0x%lx",
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n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
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}
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/*
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* "noinline" to cause control flow change and thus invalidate I$ and
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* cause refetch after modification.
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*/
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static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 *instr)
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{
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unsigned long flags;
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if (instr[0] != 0x90)
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return;
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local_irq_save(flags);
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add_nops(instr + (a->instrlen - a->padlen), a->padlen);
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local_irq_restore(flags);
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DUMP_BYTES(instr, a->instrlen, "%p: [%d:%d) optimized NOPs: ",
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instr, a->instrlen - a->padlen, a->padlen);
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}
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/*
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* Replace instructions with better alternatives for this CPU type. This runs
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* before SMP is initialized to avoid SMP problems with self modifying code.
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* This implies that asymmetric systems where APs have less capabilities than
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* the boot processor are not handled. Tough. Make sure you disable such
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* features by hand.
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*
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* Marked "noinline" to cause control flow change and thus insn cache
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* to refetch changed I$ lines.
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*/
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void __init_or_module noinline apply_alternatives(struct alt_instr *start,
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struct alt_instr *end)
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{
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struct alt_instr *a;
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u8 *instr, *replacement;
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u8 insnbuf[MAX_PATCH_LEN];
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DPRINTK("alt table %p -> %p", start, end);
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/*
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* The scan order should be from start to end. A later scanned
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* alternative code can overwrite previously scanned alternative code.
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* Some kernel functions (e.g. memcpy, memset, etc) use this order to
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* patch code.
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*
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* So be careful if you want to change the scan order to any other
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* order.
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*/
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for (a = start; a < end; a++) {
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int insnbuf_sz = 0;
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instr = (u8 *)&a->instr_offset + a->instr_offset;
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replacement = (u8 *)&a->repl_offset + a->repl_offset;
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BUG_ON(a->instrlen > sizeof(insnbuf));
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BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
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if (!boot_cpu_has(a->cpuid)) {
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if (a->padlen > 1)
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optimize_nops(a, instr);
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continue;
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}
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DPRINTK("feat: %d*32+%d, old: (%p, len: %d), repl: (%p, len: %d), pad: %d",
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a->cpuid >> 5,
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a->cpuid & 0x1f,
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instr, a->instrlen,
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replacement, a->replacementlen, a->padlen);
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DUMP_BYTES(instr, a->instrlen, "%p: old_insn: ", instr);
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DUMP_BYTES(replacement, a->replacementlen, "%p: rpl_insn: ", replacement);
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memcpy(insnbuf, replacement, a->replacementlen);
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insnbuf_sz = a->replacementlen;
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/* 0xe8 is a relative jump; fix the offset. */
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if (*insnbuf == 0xe8 && a->replacementlen == 5) {
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*(s32 *)(insnbuf + 1) += replacement - instr;
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DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
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*(s32 *)(insnbuf + 1),
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(unsigned long)instr + *(s32 *)(insnbuf + 1) + 5);
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}
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if (a->replacementlen && is_jmp(replacement[0]))
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recompute_jump(a, instr, replacement, insnbuf);
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if (a->instrlen > a->replacementlen) {
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add_nops(insnbuf + a->replacementlen,
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a->instrlen - a->replacementlen);
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insnbuf_sz += a->instrlen - a->replacementlen;
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}
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DUMP_BYTES(insnbuf, insnbuf_sz, "%p: final_insn: ", instr);
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text_poke_early(instr, insnbuf, insnbuf_sz);
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}
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}
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#ifdef CONFIG_SMP
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static void alternatives_smp_lock(const s32 *start, const s32 *end,
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u8 *text, u8 *text_end)
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{
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const s32 *poff;
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mutex_lock(&text_mutex);
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for (poff = start; poff < end; poff++) {
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u8 *ptr = (u8 *)poff + *poff;
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if (!*poff || ptr < text || ptr >= text_end)
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continue;
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/* turn DS segment override prefix into lock prefix */
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if (*ptr == 0x3e)
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text_poke(ptr, ((unsigned char []){0xf0}), 1);
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}
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mutex_unlock(&text_mutex);
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}
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static void alternatives_smp_unlock(const s32 *start, const s32 *end,
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u8 *text, u8 *text_end)
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{
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const s32 *poff;
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mutex_lock(&text_mutex);
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for (poff = start; poff < end; poff++) {
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u8 *ptr = (u8 *)poff + *poff;
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if (!*poff || ptr < text || ptr >= text_end)
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continue;
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/* turn lock prefix into DS segment override prefix */
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if (*ptr == 0xf0)
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text_poke(ptr, ((unsigned char []){0x3E}), 1);
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}
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mutex_unlock(&text_mutex);
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}
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struct smp_alt_module {
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/* what is this ??? */
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struct module *mod;
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char *name;
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/* ptrs to lock prefixes */
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const s32 *locks;
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const s32 *locks_end;
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/* .text segment, needed to avoid patching init code ;) */
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u8 *text;
|
|
u8 *text_end;
|
|
|
|
struct list_head next;
|
|
};
|
|
static LIST_HEAD(smp_alt_modules);
|
|
static DEFINE_MUTEX(smp_alt);
|
|
static bool uniproc_patched = false; /* protected by smp_alt */
|
|
|
|
void __init_or_module alternatives_smp_module_add(struct module *mod,
|
|
char *name,
|
|
void *locks, void *locks_end,
|
|
void *text, void *text_end)
|
|
{
|
|
struct smp_alt_module *smp;
|
|
|
|
mutex_lock(&smp_alt);
|
|
if (!uniproc_patched)
|
|
goto unlock;
|
|
|
|
if (num_possible_cpus() == 1)
|
|
/* Don't bother remembering, we'll never have to undo it. */
|
|
goto smp_unlock;
|
|
|
|
smp = kzalloc(sizeof(*smp), GFP_KERNEL);
|
|
if (NULL == smp)
|
|
/* we'll run the (safe but slow) SMP code then ... */
|
|
goto unlock;
|
|
|
|
smp->mod = mod;
|
|
smp->name = name;
|
|
smp->locks = locks;
|
|
smp->locks_end = locks_end;
|
|
smp->text = text;
|
|
smp->text_end = text_end;
|
|
DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
|
|
smp->locks, smp->locks_end,
|
|
smp->text, smp->text_end, smp->name);
|
|
|
|
list_add_tail(&smp->next, &smp_alt_modules);
|
|
smp_unlock:
|
|
alternatives_smp_unlock(locks, locks_end, text, text_end);
|
|
unlock:
|
|
mutex_unlock(&smp_alt);
|
|
}
|
|
|
|
void __init_or_module alternatives_smp_module_del(struct module *mod)
|
|
{
|
|
struct smp_alt_module *item;
|
|
|
|
mutex_lock(&smp_alt);
|
|
list_for_each_entry(item, &smp_alt_modules, next) {
|
|
if (mod != item->mod)
|
|
continue;
|
|
list_del(&item->next);
|
|
kfree(item);
|
|
break;
|
|
}
|
|
mutex_unlock(&smp_alt);
|
|
}
|
|
|
|
void alternatives_enable_smp(void)
|
|
{
|
|
struct smp_alt_module *mod;
|
|
|
|
/* Why bother if there are no other CPUs? */
|
|
BUG_ON(num_possible_cpus() == 1);
|
|
|
|
mutex_lock(&smp_alt);
|
|
|
|
if (uniproc_patched) {
|
|
pr_info("switching to SMP code\n");
|
|
BUG_ON(num_online_cpus() != 1);
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
|
|
clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
|
|
list_for_each_entry(mod, &smp_alt_modules, next)
|
|
alternatives_smp_lock(mod->locks, mod->locks_end,
|
|
mod->text, mod->text_end);
|
|
uniproc_patched = false;
|
|
}
|
|
mutex_unlock(&smp_alt);
|
|
}
|
|
|
|
/* Return 1 if the address range is reserved for smp-alternatives */
|
|
int alternatives_text_reserved(void *start, void *end)
|
|
{
|
|
struct smp_alt_module *mod;
|
|
const s32 *poff;
|
|
u8 *text_start = start;
|
|
u8 *text_end = end;
|
|
|
|
list_for_each_entry(mod, &smp_alt_modules, next) {
|
|
if (mod->text > text_end || mod->text_end < text_start)
|
|
continue;
|
|
for (poff = mod->locks; poff < mod->locks_end; poff++) {
|
|
const u8 *ptr = (const u8 *)poff + *poff;
|
|
|
|
if (text_start <= ptr && text_end > ptr)
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_SMP */
|
|
|
|
#ifdef CONFIG_PARAVIRT
|
|
void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
|
|
struct paravirt_patch_site *end)
|
|
{
|
|
struct paravirt_patch_site *p;
|
|
char insnbuf[MAX_PATCH_LEN];
|
|
|
|
if (noreplace_paravirt)
|
|
return;
|
|
|
|
for (p = start; p < end; p++) {
|
|
unsigned int used;
|
|
|
|
BUG_ON(p->len > MAX_PATCH_LEN);
|
|
/* prep the buffer with the original instructions */
|
|
memcpy(insnbuf, p->instr, p->len);
|
|
used = pv_init_ops.patch(p->instrtype, p->clobbers, insnbuf,
|
|
(unsigned long)p->instr, p->len);
|
|
|
|
BUG_ON(used > p->len);
|
|
|
|
/* Pad the rest with nops */
|
|
add_nops(insnbuf + used, p->len - used);
|
|
text_poke_early(p->instr, insnbuf, p->len);
|
|
}
|
|
}
|
|
extern struct paravirt_patch_site __start_parainstructions[],
|
|
__stop_parainstructions[];
|
|
#endif /* CONFIG_PARAVIRT */
|
|
|
|
void __init alternative_instructions(void)
|
|
{
|
|
/* The patching is not fully atomic, so try to avoid local interruptions
|
|
that might execute the to be patched code.
|
|
Other CPUs are not running. */
|
|
stop_nmi();
|
|
|
|
/*
|
|
* Don't stop machine check exceptions while patching.
|
|
* MCEs only happen when something got corrupted and in this
|
|
* case we must do something about the corruption.
|
|
* Ignoring it is worse than a unlikely patching race.
|
|
* Also machine checks tend to be broadcast and if one CPU
|
|
* goes into machine check the others follow quickly, so we don't
|
|
* expect a machine check to cause undue problems during to code
|
|
* patching.
|
|
*/
|
|
|
|
apply_alternatives(__alt_instructions, __alt_instructions_end);
|
|
|
|
#ifdef CONFIG_SMP
|
|
/* Patch to UP if other cpus not imminent. */
|
|
if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
|
|
uniproc_patched = true;
|
|
alternatives_smp_module_add(NULL, "core kernel",
|
|
__smp_locks, __smp_locks_end,
|
|
_text, _etext);
|
|
}
|
|
|
|
if (!uniproc_patched || num_possible_cpus() == 1)
|
|
free_init_pages("SMP alternatives",
|
|
(unsigned long)__smp_locks,
|
|
(unsigned long)__smp_locks_end);
|
|
#endif
|
|
|
|
apply_paravirt(__parainstructions, __parainstructions_end);
|
|
|
|
restart_nmi();
|
|
alternatives_patched = 1;
|
|
}
|
|
|
|
/**
|
|
* text_poke_early - Update instructions on a live kernel at boot time
|
|
* @addr: address to modify
|
|
* @opcode: source of the copy
|
|
* @len: length to copy
|
|
*
|
|
* When you use this code to patch more than one byte of an instruction
|
|
* you need to make sure that other CPUs cannot execute this code in parallel.
|
|
* Also no thread must be currently preempted in the middle of these
|
|
* instructions. And on the local CPU you need to be protected again NMI or MCE
|
|
* handlers seeing an inconsistent instruction while you patch.
|
|
*/
|
|
void *__init_or_module text_poke_early(void *addr, const void *opcode,
|
|
size_t len)
|
|
{
|
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
memcpy(addr, opcode, len);
|
|
local_irq_restore(flags);
|
|
/* Could also do a CLFLUSH here to speed up CPU recovery; but
|
|
that causes hangs on some VIA CPUs. */
|
|
return addr;
|
|
}
|
|
|
|
/**
|
|
* text_poke - Update instructions on a live kernel
|
|
* @addr: address to modify
|
|
* @opcode: source of the copy
|
|
* @len: length to copy
|
|
*
|
|
* Only atomic text poke/set should be allowed when not doing early patching.
|
|
* It means the size must be writable atomically and the address must be aligned
|
|
* in a way that permits an atomic write. It also makes sure we fit on a single
|
|
* page.
|
|
*
|
|
* Note: Must be called under text_mutex.
|
|
*/
|
|
void *text_poke(void *addr, const void *opcode, size_t len)
|
|
{
|
|
unsigned long flags;
|
|
char *vaddr;
|
|
struct page *pages[2];
|
|
int i;
|
|
|
|
if (!core_kernel_text((unsigned long)addr)) {
|
|
pages[0] = vmalloc_to_page(addr);
|
|
pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
|
|
} else {
|
|
pages[0] = virt_to_page(addr);
|
|
WARN_ON(!PageReserved(pages[0]));
|
|
pages[1] = virt_to_page(addr + PAGE_SIZE);
|
|
}
|
|
BUG_ON(!pages[0]);
|
|
local_irq_save(flags);
|
|
set_fixmap(FIX_TEXT_POKE0, page_to_phys(pages[0]));
|
|
if (pages[1])
|
|
set_fixmap(FIX_TEXT_POKE1, page_to_phys(pages[1]));
|
|
vaddr = (char *)fix_to_virt(FIX_TEXT_POKE0);
|
|
memcpy(&vaddr[(unsigned long)addr & ~PAGE_MASK], opcode, len);
|
|
clear_fixmap(FIX_TEXT_POKE0);
|
|
if (pages[1])
|
|
clear_fixmap(FIX_TEXT_POKE1);
|
|
local_flush_tlb();
|
|
sync_core();
|
|
/* Could also do a CLFLUSH here to speed up CPU recovery; but
|
|
that causes hangs on some VIA CPUs. */
|
|
for (i = 0; i < len; i++)
|
|
BUG_ON(((char *)addr)[i] != ((char *)opcode)[i]);
|
|
local_irq_restore(flags);
|
|
return addr;
|
|
}
|
|
|
|
static void do_sync_core(void *info)
|
|
{
|
|
sync_core();
|
|
}
|
|
|
|
static bool bp_patching_in_progress;
|
|
static void *bp_int3_handler, *bp_int3_addr;
|
|
|
|
int poke_int3_handler(struct pt_regs *regs)
|
|
{
|
|
/* bp_patching_in_progress */
|
|
smp_rmb();
|
|
|
|
if (likely(!bp_patching_in_progress))
|
|
return 0;
|
|
|
|
if (user_mode(regs) || regs->ip != (unsigned long)bp_int3_addr)
|
|
return 0;
|
|
|
|
/* set up the specified breakpoint handler */
|
|
regs->ip = (unsigned long) bp_int3_handler;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
/**
|
|
* text_poke_bp() -- update instructions on live kernel on SMP
|
|
* @addr: address to patch
|
|
* @opcode: opcode of new instruction
|
|
* @len: length to copy
|
|
* @handler: address to jump to when the temporary breakpoint is hit
|
|
*
|
|
* Modify multi-byte instruction by using int3 breakpoint on SMP.
|
|
* We completely avoid stop_machine() here, and achieve the
|
|
* synchronization using int3 breakpoint.
|
|
*
|
|
* The way it is done:
|
|
* - add a int3 trap to the address that will be patched
|
|
* - sync cores
|
|
* - update all but the first byte of the patched range
|
|
* - sync cores
|
|
* - replace the first byte (int3) by the first byte of
|
|
* replacing opcode
|
|
* - sync cores
|
|
*
|
|
* Note: must be called under text_mutex.
|
|
*/
|
|
void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
|
|
{
|
|
unsigned char int3 = 0xcc;
|
|
|
|
bp_int3_handler = handler;
|
|
bp_int3_addr = (u8 *)addr + sizeof(int3);
|
|
bp_patching_in_progress = true;
|
|
/*
|
|
* Corresponding read barrier in int3 notifier for
|
|
* making sure the in_progress flags is correctly ordered wrt.
|
|
* patching
|
|
*/
|
|
smp_wmb();
|
|
|
|
text_poke(addr, &int3, sizeof(int3));
|
|
|
|
on_each_cpu(do_sync_core, NULL, 1);
|
|
|
|
if (len - sizeof(int3) > 0) {
|
|
/* patch all but the first byte */
|
|
text_poke((char *)addr + sizeof(int3),
|
|
(const char *) opcode + sizeof(int3),
|
|
len - sizeof(int3));
|
|
/*
|
|
* According to Intel, this core syncing is very likely
|
|
* not necessary and we'd be safe even without it. But
|
|
* better safe than sorry (plus there's not only Intel).
|
|
*/
|
|
on_each_cpu(do_sync_core, NULL, 1);
|
|
}
|
|
|
|
/* patch the first byte */
|
|
text_poke(addr, opcode, sizeof(int3));
|
|
|
|
on_each_cpu(do_sync_core, NULL, 1);
|
|
|
|
bp_patching_in_progress = false;
|
|
smp_wmb();
|
|
|
|
return addr;
|
|
}
|
|
|