![Linus Torvalds](/assets/img/avatar_default.png)
200 commits and noteworthy changes for most architectures. * ARM: - GICv3 save/restore - cache flushing fixes - working MSI injection for GICv3 ITS - physical timer emulation * MIPS: - various improvements under the hood - support for SMP guests - a large rewrite of MMU emulation. KVM MIPS can now use MMU notifiers to support copy-on-write, KSM, idle page tracking, swapping, ballooning and everything else. KVM_CAP_READONLY_MEM is also supported, so that writes to some memory regions can be treated as MMIO. The new MMU also paves the way for hardware virtualization support. * PPC: - support for POWER9 using the radix-tree MMU for host and guest - resizable hashed page table - bugfixes. * s390: expose more features to the guest - more SIMD extensions - instruction execution protection - ESOP2 * x86: - improved hashing in the MMU - faster PageLRU tracking for Intel CPUs without EPT A/D bits - some refactoring of nested VMX entry/exit code, preparing for live migration support of nested hypervisors - expose yet another AVX512 CPUID bit - host-to-guest PTP support - refactoring of interrupt injection, with some optimizations thrown in and some duct tape removed. - remove lazy FPU handling - optimizations of user-mode exits - optimizations of vcpu_is_preempted() for KVM guests * generic: - alternative signaling mechanism that doesn't pound on tsk->sighand->siglock -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQEcBAABAgAGBQJYral1AAoJEL/70l94x66DbNgH/Rx8YXuidFq2fe3RWOvld3RK 85OM/D5g38cTLpBE0/sJpcvX34iYN8U/l5foCZwpxB+83GHEk2Cr57JyfTogdaAJ x8dBhHKQCA/HxSQUQLN6nFqRV+yT8WUR92Fhqx82+80BSen5Yzcfee/TDoW6T1IW g8CYgX9FrRaGOX066ImAuUfdAdUVjyssfs9VttDTX+HiusPeuBPx/wsRe1ZEEPlH vnltIJQb1ETV2GOZLUojKjzH6aZkjIl29XxjkYii9JTUornClG0DfW+5QT3uLrB5 gJ+G+Zmpsq8ZBx9jNDtAi7sFsoPY1Mzf+JPNCGXBra2sP2GrBAuXcxmgznRYltQ= =8IIp -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm Pull KVM updates from Paolo Bonzini: "4.11 is going to be a relatively large release for KVM, with a little over 200 commits and noteworthy changes for most architectures. ARM: - GICv3 save/restore - cache flushing fixes - working MSI injection for GICv3 ITS - physical timer emulation MIPS: - various improvements under the hood - support for SMP guests - a large rewrite of MMU emulation. KVM MIPS can now use MMU notifiers to support copy-on-write, KSM, idle page tracking, swapping, ballooning and everything else. KVM_CAP_READONLY_MEM is also supported, so that writes to some memory regions can be treated as MMIO. The new MMU also paves the way for hardware virtualization support. PPC: - support for POWER9 using the radix-tree MMU for host and guest - resizable hashed page table - bugfixes. s390: - expose more features to the guest - more SIMD extensions - instruction execution protection - ESOP2 x86: - improved hashing in the MMU - faster PageLRU tracking for Intel CPUs without EPT A/D bits - some refactoring of nested VMX entry/exit code, preparing for live migration support of nested hypervisors - expose yet another AVX512 CPUID bit - host-to-guest PTP support - refactoring of interrupt injection, with some optimizations thrown in and some duct tape removed. - remove lazy FPU handling - optimizations of user-mode exits - optimizations of vcpu_is_preempted() for KVM guests generic: - alternative signaling mechanism that doesn't pound on tsk->sighand->siglock" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (195 commits) x86/kvm: Provide optimized version of vcpu_is_preempted() for x86-64 x86/paravirt: Change vcp_is_preempted() arg type to long KVM: VMX: use correct vmcs_read/write for guest segment selector/base x86/kvm/vmx: Defer TR reload after VM exit x86/asm/64: Drop __cacheline_aligned from struct x86_hw_tss x86/kvm/vmx: Simplify segment_base() x86/kvm/vmx: Get rid of segment_base() on 64-bit kernels x86/kvm/vmx: Don't fetch the TSS base from the GDT x86/asm: Define the kernel TSS limit in a macro kvm: fix page struct leak in handle_vmon KVM: PPC: Book3S HV: Disable HPT resizing on POWER9 for now KVM: Return an error code only as a constant in kvm_get_dirty_log() KVM: Return an error code only as a constant in kvm_get_dirty_log_protect() KVM: Return directly after a failed copy_from_user() in kvm_vm_compat_ioctl() KVM: x86: remove code for lazy FPU handling KVM: race-free exit from KVM_RUN without POSIX signals KVM: PPC: Book3S HV: Turn "KVM guest htab" message into a debug message KVM: PPC: Book3S PR: Ratelimit copy data failure error messages KVM: Support vCPU-based gfn->hva cache KVM: use separate generations for each address space ...
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
/*
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* Split spinlock implementation out into its own file, so it can be
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* compiled in a FTRACE-compatible way.
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*/
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#include <linux/spinlock.h>
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#include <linux/export.h>
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#include <linux/jump_label.h>
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#include <asm/paravirt.h>
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__visible void __native_queued_spin_unlock(struct qspinlock *lock)
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{
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native_queued_spin_unlock(lock);
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}
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PV_CALLEE_SAVE_REGS_THUNK(__native_queued_spin_unlock);
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bool pv_is_native_spin_unlock(void)
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{
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return pv_lock_ops.queued_spin_unlock.func ==
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__raw_callee_save___native_queued_spin_unlock;
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}
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__visible bool __native_vcpu_is_preempted(long cpu)
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{
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return false;
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}
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PV_CALLEE_SAVE_REGS_THUNK(__native_vcpu_is_preempted);
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bool pv_is_native_vcpu_is_preempted(void)
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{
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return pv_lock_ops.vcpu_is_preempted.func ==
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__raw_callee_save___native_vcpu_is_preempted;
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}
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struct pv_lock_ops pv_lock_ops = {
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#ifdef CONFIG_SMP
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.queued_spin_lock_slowpath = native_queued_spin_lock_slowpath,
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.queued_spin_unlock = PV_CALLEE_SAVE(__native_queued_spin_unlock),
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.wait = paravirt_nop,
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.kick = paravirt_nop,
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.vcpu_is_preempted = PV_CALLEE_SAVE(__native_vcpu_is_preempted),
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#endif /* SMP */
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};
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EXPORT_SYMBOL(pv_lock_ops);
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