eb785bef68
As usual, this is the largest branch, though this time a little under half of the total changes with 307 individual non-merge changesets. The largest changes are the addition of new machines, in particular the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support for the old i.MX1 platform. Other changes include - at91: various sam9 and sama5 updates - exynos: much extended Peach Pi/Pit (Chromebook 2) support - keystone: new peripherals - meson: added DT for meson6 SoC - mvebu: new device support for Armada 370/375 - qcom: improved support for IPQ8064 and MSM8x60 - rockchip: much improved support for rk3288 - shmobile: lots of updates all over the place - sunxi: dts license change - sunxi: more a23 device support - vexpress: CLCD DT description -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAVDWVG2CrR//JCVInAQJmARAAnU2I4VpJHlBeHC4CYr/GdRq0NqiFvQ38 7N/zevUI4l150DtejltbOX71JGM9vD3hq8VXZYBCEpTbG4el9PzAq28Fomtt4tmC PGbczQY8ZMvY1/MOT3XLZAd3TSUL0TZRt97t9bdLif6QyPafel5o2pd8D2OG7h+L Awtyk9LobT9jU3muFX3ZUfB3Gg2sNKphZjox9Le3gVjGd6g5teEqqMAehK2Y7ArJ kixrKck4vgduDdZe59o2yApAUsfIQv/joqu68jv3MUQrKmk4s543+rIdGDuLF5bz mEo7qtMXujoNaF3CyLYNEF2ZExIOJDdtmrwjHY8oKIFtIeI/faIJmeSChwa6794t Njj5bbnL0Pt61l4gUSFk2hUFo28gpiEB+Mm0R4E1hdoG15Iv6E+lpy44EmEmfz1c 9h0sATNGUrz18IrUk7jI1WwIaEJUwkbZ+8wKuWtvH+Z+mFA4ZlDykVcnVuELixpb vKmI3kcmEw2RsJjkYq3LcgXXQevE4mHRR1ow59yXTY6OR1LmVb7odKUwbrweofQO eytVb1deMeYXrBXT5/j6WmrlyDbYcuGsjO4WidT+zwYUiAMCE6bTpNwUWqumVEUv LjCBaN6BRIb89EBwt4xIvIu7ir9hNNRZnD8aa4afSzIYxknzZy73pjjT2+wu7jbU m15TwYyQG4E= =2Sq1 -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Arnd Bergmann: "As usual, this is the largest branch, though this time a little under half of the total changes with 307 individual non-merge changesets. The largest changes are the addition of new machines, in particular the Tegra based Chromebook, the Renesas r8a7794 SoC, and DT support for the old i.MX1 platform. Other changes include - at91: various sam9 and sama5 updates - exynos: much extended Peach Pi/Pit (Chromebook 2) support - keystone: new peripherals - meson: added DT for meson6 SoC - mvebu: new device support for Armada 370/375 - qcom: improved support for IPQ8064 and MSM8x60 - rockchip: much improved support for rk3288 - shmobile: lots of updates all over the place - sunxi: dts license change - sunxi: more a23 device support - vexpress: CLCD DT description" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (308 commits) ARM: DTS: meson: update DTSI to add watchdog node ARM: dts: keystone-k2l: fix mdio io start address ARM: dts: keystone-k2e: fix mdio io start address ARM: dts: keystone-k2e: update usb1 node for dma properties ARM: dts: keystone: fix io range for usb_phy0 Revert "Merge tag 'hix5hd2-dt-for-3.18' of git://github.com/hisilicon/linux-hisi into next/dt" Revert "ARM: dts: hix5hd2: add wdg node" ARM: dts: add rk3288 i2s controller ARM: vexpress: Add CLCD Device Tree properties ARM: bcm2835: add I2S pinctrl to device tree ARM: meson: documentation: add bindings documentation ARM: meson: dts: add basic Meson/Meson6/Meson6-atv1200 DTSI/DTS ARM: dts: mt6589: Change compatible string for GIC ARM: dts: mediatek: Add compatible property for aquaris5 ARM: dts: mt6589-aquaris5: Add boot argument earlyprintk ARM: dts: mt6589: Fix typo in GIC unit address ARM: dts: Build dtb for Mediatek board ARM: dts: keystone: fix bindings for pcie and usb clock nodes ARM: dts: keystone: k2l: Fix chip selects for SPI devices ARM: dts: keystone: add dsp gpio controllers nodes ...
1218 lines
36 KiB
Plaintext
1218 lines
36 KiB
Plaintext
/*
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* Device Tree Source for the r8a7791 SoC
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*
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2013-2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Cogent Embedded Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r8a7791-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r8a7791";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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spi0 = &qspi;
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spi1 = &msiof0;
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spi2 = &msiof1;
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spi3 = &msiof2;
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vin0 = &vin0;
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vin1 = &vin1;
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vin2 = &vin2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1500000000>;
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voltage-tolerance = <1>; /* 1% */
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clocks = <&cpg_clocks R8A7791_CLK_Z>;
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1500000 1000000>,
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<1312500 1000000>,
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<1125000 1000000>,
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< 937500 1000000>,
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< 750000 1000000>,
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< 375000 1000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1500000000>;
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x1000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
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};
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gpio7: gpio@e6055800 {
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compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
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reg = <0 0xe6055800 0 0x50>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 224 26>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
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};
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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cmt0: timer@ffca0000 {
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compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
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reg = <0 0xffca0000 0 0x1004>;
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interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
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<0 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
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clock-names = "fck";
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renesas,channels-mask = <0x60>;
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status = "disabled";
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};
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cmt1: timer@e6130000 {
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compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
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reg = <0 0xe6130000 0 0x1004>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 124 IRQ_TYPE_LEVEL_HIGH>,
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<0 125 IRQ_TYPE_LEVEL_HIGH>,
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<0 126 IRQ_TYPE_LEVEL_HIGH>,
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<0 127 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
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clock-names = "fck";
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renesas,channels-mask = <0xff>;
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status = "disabled";
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};
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irqc0: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7791", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 17 IRQ_TYPE_LEVEL_HIGH>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
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0 200 IRQ_TYPE_LEVEL_HIGH
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0 201 IRQ_TYPE_LEVEL_HIGH
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0 202 IRQ_TYPE_LEVEL_HIGH
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0 203 IRQ_TYPE_LEVEL_HIGH
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0 204 IRQ_TYPE_LEVEL_HIGH
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0 205 IRQ_TYPE_LEVEL_HIGH
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0 206 IRQ_TYPE_LEVEL_HIGH
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0 207 IRQ_TYPE_LEVEL_HIGH
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0 208 IRQ_TYPE_LEVEL_HIGH
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0 209 IRQ_TYPE_LEVEL_HIGH
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0 210 IRQ_TYPE_LEVEL_HIGH
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0 211 IRQ_TYPE_LEVEL_HIGH
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0 212 IRQ_TYPE_LEVEL_HIGH
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0 213 IRQ_TYPE_LEVEL_HIGH
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0 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
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clock-names = "fck";
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
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0 216 IRQ_TYPE_LEVEL_HIGH
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0 217 IRQ_TYPE_LEVEL_HIGH
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0 218 IRQ_TYPE_LEVEL_HIGH
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0 219 IRQ_TYPE_LEVEL_HIGH
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0 308 IRQ_TYPE_LEVEL_HIGH
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0 309 IRQ_TYPE_LEVEL_HIGH
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0 310 IRQ_TYPE_LEVEL_HIGH
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0 311 IRQ_TYPE_LEVEL_HIGH
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0 312 IRQ_TYPE_LEVEL_HIGH
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0 313 IRQ_TYPE_LEVEL_HIGH
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0 314 IRQ_TYPE_LEVEL_HIGH
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0 315 IRQ_TYPE_LEVEL_HIGH
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0 316 IRQ_TYPE_LEVEL_HIGH
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0 317 IRQ_TYPE_LEVEL_HIGH
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0 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
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clock-names = "fck";
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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/* The memory map in the User's Manual maps the cores to bus numbers */
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i2c0: i2c@e6508000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6518000 0 0x40>;
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interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
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status = "disabled";
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};
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i2c2: i2c@e6530000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6530000 0 0x40>;
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interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
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status = "disabled";
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};
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i2c3: i2c@e6540000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6540000 0 0x40>;
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interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
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status = "disabled";
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};
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i2c4: i2c@e6520000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6520000 0 0x40>;
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interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
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status = "disabled";
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};
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i2c5: i2c@e6528000 {
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/* doesn't need pinmux */
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a7791";
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reg = <0 0xe6528000 0 0x40>;
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interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
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status = "disabled";
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};
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i2c6: i2c@e60b0000 {
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/* doesn't need pinmux */
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#address-cells = <1>;
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#size-cells = <0>;
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|
compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
|
|
reg = <0 0xe60b0000 0 0x425>;
|
|
interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@e6500000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
|
|
reg = <0 0xe6500000 0 0x425>;
|
|
interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@e6510000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
|
|
reg = <0 0xe6510000 0 0x425>;
|
|
interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pfc: pfc@e6060000 {
|
|
compatible = "renesas,pfc-r8a7791";
|
|
reg = <0 0xe6060000 0 0x250>;
|
|
#gpio-range-cells = <3>;
|
|
};
|
|
|
|
sdhi0: sd@ee100000 {
|
|
compatible = "renesas,sdhi-r8a7791";
|
|
reg = <0 0xee100000 0 0x200>;
|
|
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: sd@ee140000 {
|
|
compatible = "renesas,sdhi-r8a7791";
|
|
reg = <0 0xee140000 0 0x100>;
|
|
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: sd@ee160000 {
|
|
compatible = "renesas,sdhi-r8a7791";
|
|
reg = <0 0xee160000 0 0x100>;
|
|
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa0: serial@e6c40000 {
|
|
compatible = "renesas,scifa-r8a7791", "renesas,scifa";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa1: serial@e6c50000 {
|
|
compatible = "renesas,scifa-r8a7791", "renesas,scifa";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa2: serial@e6c60000 {
|
|
compatible = "renesas,scifa-r8a7791", "renesas,scifa";
|
|
reg = <0 0xe6c60000 0 64>;
|
|
interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa3: serial@e6c70000 {
|
|
compatible = "renesas,scifa-r8a7791", "renesas,scifa";
|
|
reg = <0 0xe6c70000 0 64>;
|
|
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa4: serial@e6c78000 {
|
|
compatible = "renesas,scifa-r8a7791", "renesas,scifa";
|
|
reg = <0 0xe6c78000 0 64>;
|
|
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa5: serial@e6c80000 {
|
|
compatible = "renesas,scifa-r8a7791", "renesas,scifa";
|
|
reg = <0 0xe6c80000 0 64>;
|
|
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb0: serial@e6c20000 {
|
|
compatible = "renesas,scifb-r8a7791", "renesas,scifb";
|
|
reg = <0 0xe6c20000 0 64>;
|
|
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb1: serial@e6c30000 {
|
|
compatible = "renesas,scifb-r8a7791", "renesas,scifb";
|
|
reg = <0 0xe6c30000 0 64>;
|
|
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb2: serial@e6ce0000 {
|
|
compatible = "renesas,scifb-r8a7791", "renesas,scifb";
|
|
reg = <0 0xe6ce0000 0 64>;
|
|
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e58000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6e58000 0 64>;
|
|
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6ea8000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6ea8000 0 64>;
|
|
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6ee0000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6ee0000 0 64>;
|
|
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6ee8000 {
|
|
compatible = "renesas,scif-r8a7791", "renesas,scif";
|
|
reg = <0 0xe6ee8000 0 64>;
|
|
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e62c0000 {
|
|
compatible = "renesas,hscif-r8a7791", "renesas,hscif";
|
|
reg = <0 0xe62c0000 0 96>;
|
|
interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif1: serial@e62c8000 {
|
|
compatible = "renesas,hscif-r8a7791", "renesas,hscif";
|
|
reg = <0 0xe62c8000 0 96>;
|
|
interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif2: serial@e62d0000 {
|
|
compatible = "renesas,hscif-r8a7791", "renesas,hscif";
|
|
reg = <0 0xe62d0000 0 96>;
|
|
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
|
|
clock-names = "sci_ick";
|
|
status = "disabled";
|
|
};
|
|
|
|
ether: ethernet@ee700000 {
|
|
compatible = "renesas,ether-r8a7791";
|
|
reg = <0 0xee700000 0 0x400>;
|
|
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
|
|
phy-mode = "rmii";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata0: sata@ee300000 {
|
|
compatible = "renesas,sata-r8a7791";
|
|
reg = <0 0xee300000 0 0x2000>;
|
|
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata1: sata@ee500000 {
|
|
compatible = "renesas,sata-r8a7791";
|
|
reg = <0 0xee500000 0 0x2000>;
|
|
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin0: video@e6ef0000 {
|
|
compatible = "renesas,vin-r8a7791";
|
|
clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
|
|
reg = <0 0xe6ef0000 0 0x1000>;
|
|
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin1: video@e6ef1000 {
|
|
compatible = "renesas,vin-r8a7791";
|
|
clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
|
|
reg = <0 0xe6ef1000 0 0x1000>;
|
|
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin2: video@e6ef2000 {
|
|
compatible = "renesas,vin-r8a7791";
|
|
clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
|
|
reg = <0 0xe6ef2000 0 0x1000>;
|
|
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
/* External root clock */
|
|
extal_clk: extal_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overriden by the board. */
|
|
clock-frequency = <0>;
|
|
clock-output-names = "extal";
|
|
};
|
|
|
|
/*
|
|
* The external audio clocks are configured as 0 Hz fixed frequency clocks by
|
|
* default. Boards that provide audio clocks should override them.
|
|
*/
|
|
audio_clk_a: audio_clk_a {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
clock-output-names = "audio_clk_a";
|
|
};
|
|
audio_clk_b: audio_clk_b {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
clock-output-names = "audio_clk_b";
|
|
};
|
|
audio_clk_c: audio_clk_c {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
clock-output-names = "audio_clk_c";
|
|
};
|
|
|
|
/* External PCIe clock - can be overridden by the board */
|
|
pcie_bus_clk: pcie_bus_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <100000000>;
|
|
clock-output-names = "pcie_bus";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* Special CPG clocks */
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
|
compatible = "renesas,r8a7791-cpg-clocks",
|
|
"renesas,rcar-gen2-cpg-clocks";
|
|
reg = <0 0xe6150000 0 0x1000>;
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <1>;
|
|
clock-output-names = "main", "pll0", "pll1", "pll3",
|
|
"lb", "qspi", "sdh", "sd0", "z";
|
|
};
|
|
|
|
/* Variable factor clocks */
|
|
sd1_clk: sd2_clk@e6150078 {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150078 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "sd1";
|
|
};
|
|
sd2_clk: sd3_clk@e615026c {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe615026c 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "sd2";
|
|
};
|
|
mmc0_clk: mmc0_clk@e6150240 {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150240 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "mmc0";
|
|
};
|
|
ssp_clk: ssp_clk@e6150248 {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe6150248 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "ssp";
|
|
};
|
|
ssprs_clk: ssprs_clk@e615024c {
|
|
compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0 0xe615024c 0 4>;
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "ssprs";
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
pll1_div2_clk: pll1_div2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "pll1_div2";
|
|
};
|
|
zg_clk: zg_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <3>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zg";
|
|
};
|
|
zx_clk: zx_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <3>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zx";
|
|
};
|
|
zs_clk: zs_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <6>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zs";
|
|
};
|
|
hp_clk: hp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "hp";
|
|
};
|
|
i_clk: i_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "i";
|
|
};
|
|
b_clk: b_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <12>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "b";
|
|
};
|
|
p_clk: p_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <24>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "p";
|
|
};
|
|
cl_clk: cl_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <48>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "cl";
|
|
};
|
|
m2_clk: m2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "m2";
|
|
};
|
|
imp_clk: imp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "imp";
|
|
};
|
|
rclk_clk: rclk_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(48 * 1024)>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "rclk";
|
|
};
|
|
oscclk_clk: oscclk_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <(12 * 1024)>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "oscclk";
|
|
};
|
|
zb3_clk: zb3_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zb3";
|
|
};
|
|
zb3d2_clk: zb3d2_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "zb3d2";
|
|
};
|
|
ddr_clk: ddr_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
|
|
#clock-cells = <0>;
|
|
clock-div = <8>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "ddr";
|
|
};
|
|
mp_clk: mp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&pll1_div2_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <15>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "mp";
|
|
};
|
|
cp_clk: cp_clk {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&extal_clk>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
clock-output-names = "cp";
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
|
|
clocks = <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
|
|
clock-output-names = "msiof0";
|
|
};
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
|
|
clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
|
|
<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
|
|
R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
|
|
R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
|
|
>;
|
|
clock-output-names =
|
|
"jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
|
|
"vsp1-du0", "vsp1-sy";
|
|
};
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&mp_clk>, <&mp_clk>, <&mp_clk>,
|
|
<&zs_clk>, <&zs_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
|
|
R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
|
|
R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
|
|
R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
|
|
>;
|
|
clock-output-names =
|
|
"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
|
|
"scifb1", "msiof1", "scifb2",
|
|
"sys-dmac1", "sys-dmac0";
|
|
};
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
|
clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
|
|
<&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
|
|
R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
|
|
R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
|
|
>;
|
|
clock-output-names =
|
|
"tpu0", "sdhi2", "sdhi1", "sdhi0",
|
|
"mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
|
|
};
|
|
mstp5_clks: mstp5_clks@e6150144 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
|
|
clocks = <&extal_clk>, <&p_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
|
|
clock-output-names = "thermal", "pwm";
|
|
};
|
|
mstp7_clks: mstp7_clks@e615014c {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
|
|
<&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
<&zx_clk>, <&zx_clk>, <&zx_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
|
|
R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
|
|
R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
|
|
R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
|
|
R8A7791_CLK_LVDS0
|
|
>;
|
|
clock-output-names =
|
|
"ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
|
|
"scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
|
|
};
|
|
mstp8_clks: mstp8_clks@e6150990 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
|
|
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
|
|
<&zs_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
|
|
R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
|
|
>;
|
|
clock-output-names =
|
|
"vin2", "vin1", "vin0", "ether", "sata1", "sata0";
|
|
};
|
|
mstp9_clks: mstp9_clks@e6150994 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
|
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
|
<&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
|
|
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
|
<&hp_clk>, <&hp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
|
|
R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
|
|
R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
|
|
R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
|
|
R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
|
|
>;
|
|
clock-output-names =
|
|
"gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
|
|
"rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
|
|
"i2c1", "i2c0";
|
|
};
|
|
mstp10_clks: mstp10_clks@e6150998 {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
|
|
clocks = <&p_clk>,
|
|
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
|
|
<&p_clk>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
|
|
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
R8A7791_CLK_SSI_ALL
|
|
R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
|
|
R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
|
|
R8A7791_CLK_SCU_ALL
|
|
R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
|
|
R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
|
|
R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
|
|
>;
|
|
clock-output-names =
|
|
"ssi-all",
|
|
"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
|
|
"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
|
|
"scu-all",
|
|
"scu-dvc1", "scu-dvc0",
|
|
"scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
|
|
"scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
|
|
};
|
|
mstp11_clks: mstp11_clks@e615099c {
|
|
compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
|
|
clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
|
|
#clock-cells = <1>;
|
|
renesas,clock-indices = <
|
|
R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
|
|
>;
|
|
clock-output-names = "scifa3", "scifa4", "scifa5";
|
|
};
|
|
};
|
|
|
|
qspi: spi@e6b10000 {
|
|
compatible = "renesas,qspi-r8a7791", "renesas,qspi";
|
|
reg = <0 0xe6b10000 0 0x2c>;
|
|
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
|
|
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
|
|
dma-names = "tx", "rx";
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e20000 {
|
|
compatible = "renesas,msiof-r8a7791";
|
|
reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
|
|
interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
|
|
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6e10000 {
|
|
compatible = "renesas,msiof-r8a7791";
|
|
reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
|
|
interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
|
|
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6e00000 {
|
|
compatible = "renesas,msiof-r8a7791";
|
|
reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
|
|
interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
|
|
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pci0: pci@ee090000 {
|
|
compatible = "renesas,pci-r8a7791";
|
|
device_type = "pci";
|
|
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
|
reg = <0 0xee090000 0 0xc00>,
|
|
<0 0xee080000 0 0x1100>;
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
|
|
bus-range = <0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
|
|
0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
|
|
0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pci1: pci@ee0d0000 {
|
|
compatible = "renesas,pci-r8a7791";
|
|
device_type = "pci";
|
|
clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
|
|
reg = <0 0xee0d0000 0 0xc00>,
|
|
<0 0xee0c0000 0 0x1100>;
|
|
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
|
|
bus-range = <1 1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
|
|
interrupt-map-mask = <0xff00 0 0 0x7>;
|
|
interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
|
|
0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
|
|
0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pciec: pcie@fe000000 {
|
|
compatible = "renesas,pcie-r8a7791";
|
|
reg = <0 0xfe000000 0 0x80000>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x00 0xff>;
|
|
device_type = "pci";
|
|
ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
|
|
0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
|
|
0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
|
|
0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
|
|
/* Map all possible DDR as inbound ranges */
|
|
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
|
|
0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
|
|
interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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status = "disabled";
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};
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|
|
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rcar_sound: rcar_sound@0xec500000 {
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#sound-dai-cells = <1>;
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compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
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reg = <0 0xec500000 0 0x1000>, /* SCU */
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<0 0xec5a0000 0 0x100>, /* ADG */
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<0 0xec540000 0 0x1000>, /* SSIU */
|
|
<0 0xec541000 0 0x1280>; /* SSI */
|
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clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
|
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<&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
|
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<&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
|
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<&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
|
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<&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
|
|
<&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
|
|
<&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
|
|
<&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
|
|
clock-names = "ssi-all",
|
|
"ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
|
|
"ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
|
|
"src.9", "src.8", "src.7", "src.6", "src.5",
|
|
"src.4", "src.3", "src.2", "src.1", "src.0",
|
|
"dvc.0", "dvc.1",
|
|
"clk_a", "clk_b", "clk_c", "clk_i";
|
|
|
|
status = "disabled";
|
|
|
|
rcar_sound,dvc {
|
|
dvc0: dvc@0 { };
|
|
dvc1: dvc@1 { };
|
|
};
|
|
|
|
rcar_sound,src {
|
|
src0: src@0 { };
|
|
src1: src@1 { };
|
|
src2: src@2 { };
|
|
src3: src@3 { };
|
|
src4: src@4 { };
|
|
src5: src@5 { };
|
|
src6: src@6 { };
|
|
src7: src@7 { };
|
|
src8: src@8 { };
|
|
src9: src@9 { };
|
|
};
|
|
|
|
rcar_sound,ssi {
|
|
ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
|
|
ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
|
|
};
|
|
};
|
|
};
|