1bb772679f
The choice is between looping over the physical range and performing single cache line operations, or to map highmem pages somewhere, as cache range ops are possible only on virtual addresses. Because L2 range ops are much faster, we go with the later by factoring the physical-to-virtual address conversion and use a fixmap entry for it in the HIGHMEM case. Possible future optimizations to avoid the pte setup cost: - do the pte setup for highmem pages only - determine a threshold for doing a line-by-line processing on physical addresses when the range is small Signed-off-by: Nicolas Pitre <nico@marvell.com>
26 lines
357 B
C
26 lines
357 B
C
#ifndef __ARM_KMAP_TYPES_H
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#define __ARM_KMAP_TYPES_H
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/*
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* This is the "bare minimum". AIO seems to require this.
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*/
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enum km_type {
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KM_BOUNCE_READ,
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KM_SKB_SUNRPC_DATA,
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KM_SKB_DATA_SOFTIRQ,
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KM_USER0,
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KM_USER1,
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KM_BIO_SRC_IRQ,
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KM_BIO_DST_IRQ,
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KM_PTE0,
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KM_PTE1,
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KM_IRQ0,
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KM_IRQ1,
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KM_SOFTIRQ0,
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KM_SOFTIRQ1,
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KM_L2_CACHE,
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KM_TYPE_NR
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};
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#endif
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