![dmitry pervushin](/assets/img/avatar_default.png)
Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
553 lines
14 KiB
C
553 lines
14 KiB
C
/*
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* Freescale STMP378X/STMP378X Pin Multiplexing
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*
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* Author: Vladislav Buzov <vbuzov@embeddedalley.com>
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*
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* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#define DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/sysdev.h>
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#include <linux/string.h>
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#include <linux/bitops.h>
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#include <linux/sysdev.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <mach/regs-pinctrl.h>
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#include <mach/pins.h>
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#include <mach/pinmux.h>
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#define NR_BANKS ARRAY_SIZE(pinmux_banks)
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static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
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[0] = {
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.hw_muxsel = {
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
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},
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.hw_drive = {
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
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},
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.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
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.functions = { 0x0, 0x1, 0x2, 0x3 },
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.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
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.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
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.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
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.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
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.irq = IRQ_GPIO0,
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.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
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.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
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.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
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.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
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.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
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},
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[1] = {
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.hw_muxsel = {
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
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},
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.hw_drive = {
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
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},
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.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
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.functions = { 0x0, 0x1, 0x2, 0x3 },
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.strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
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.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
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.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
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.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
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.irq = IRQ_GPIO1,
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.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
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.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
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.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
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.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
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.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
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},
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[2] = {
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.hw_muxsel = {
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
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},
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.hw_drive = {
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
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},
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.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
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.functions = { 0x0, 0x1, 0x2, 0x3 },
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.strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
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.hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
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.hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
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.hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
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.irq = IRQ_GPIO2,
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.pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
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.irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
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.irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
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.irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
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.irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
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},
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[3] = {
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.hw_muxsel = {
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
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REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
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},
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.hw_drive = {
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
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REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
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NULL,
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},
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.hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
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.functions = {0x0, 0x1, 0x2, 0x3},
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.strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
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},
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};
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static inline struct stmp3xxx_pinmux_bank *
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stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
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{
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unsigned b, p;
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b = STMP3XXX_PINID_TO_BANK(id);
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p = STMP3XXX_PINID_TO_PINNUM(id);
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BUG_ON(b >= NR_BANKS);
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if (bank)
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*bank = b;
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if (pin)
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*pin = p;
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return &pinmux_banks[b];
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}
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/* Check if requested pin is owned by caller */
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static int stmp3xxx_check_pin(unsigned id, const char *label)
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{
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unsigned pin;
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struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
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if (!test_bit(pin, &pm->pin_map)) {
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printk(KERN_WARNING
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"%s: Accessing free pin %x, caller %s\n",
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__func__, id, label);
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return -EINVAL;
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}
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if (label && pm->pin_labels[pin] &&
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strcmp(label, pm->pin_labels[pin])) {
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printk(KERN_WARNING
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"%s: Wrong pin owner %x, caller %s owner %s\n",
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__func__, id, label, pm->pin_labels[pin]);
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return -EINVAL;
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}
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return 0;
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}
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void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
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const char *label)
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{
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struct stmp3xxx_pinmux_bank *pbank;
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void __iomem *hwdrive;
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u32 shift, val;
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u32 bank, pin;
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pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
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pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
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bank, pin, strength);
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hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
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shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
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val = pbank->strengths[strength];
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if (val == 0xff) {
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printk(KERN_WARNING
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"%s: strength is not supported for bank %d, caller %s",
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__func__, bank, label);
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return;
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}
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if (stmp3xxx_check_pin(id, label))
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return;
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pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
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val << shift, hwdrive);
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stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
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stmp3xxx_setl(val << shift, hwdrive);
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}
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void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
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const char *label)
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{
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struct stmp3xxx_pinmux_bank *pbank;
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void __iomem *hwdrive;
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u32 shift;
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u32 bank, pin;
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pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
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pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
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bank, pin, voltage);
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hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
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shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
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if (stmp3xxx_check_pin(id, label))
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return;
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pr_debug("%s: changing 0x%x bit in 0x%p register\n",
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__func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
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if (voltage == PIN_1_8V)
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stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
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else
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stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
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}
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void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
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{
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struct stmp3xxx_pinmux_bank *pbank;
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void __iomem *hwpull;
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u32 bank, pin;
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pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
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pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
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bank, pin, enable);
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hwpull = pbank->hw_pull;
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if (stmp3xxx_check_pin(id, label))
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return;
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pr_debug("%s: changing 0x%x bit in 0x%p register\n",
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__func__, 1 << pin, hwpull);
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if (enable)
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stmp3xxx_setl(1 << pin, hwpull);
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else
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stmp3xxx_clearl(1 << pin, hwpull);
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}
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int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
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{
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struct stmp3xxx_pinmux_bank *pbank;
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u32 bank, pin;
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int ret = 0;
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pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
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pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
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bank, pin, fun);
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if (test_bit(pin, &pbank->pin_map)) {
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printk(KERN_WARNING
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"%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
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__func__, bank, pin, label, pbank->pin_labels[pin]);
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return -EBUSY;
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}
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set_bit(pin, &pbank->pin_map);
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pbank->pin_labels[pin] = label;
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stmp3xxx_set_pin_type(id, fun);
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return ret;
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}
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void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
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{
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struct stmp3xxx_pinmux_bank *pbank;
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void __iomem *hwmux;
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u32 shift, val;
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u32 bank, pin;
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pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
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hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
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shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
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val = pbank->functions[fun];
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shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
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pr_debug("%s: writing 0x%x to 0x%p register\n",
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__func__, val << shift, hwmux);
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stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
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stmp3xxx_setl(val << shift, hwmux);
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}
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void stmp3xxx_release_pin(unsigned id, const char *label)
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{
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struct stmp3xxx_pinmux_bank *pbank;
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u32 bank, pin;
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pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
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pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
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if (stmp3xxx_check_pin(id, label))
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return;
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clear_bit(pin, &pbank->pin_map);
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pbank->pin_labels[pin] = NULL;
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}
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int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
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{
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struct pin_desc *pin;
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int p;
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int err = 0;
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/* Allocate and configure pins */
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for (p = 0; p < pin_group->nr_pins; p++) {
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pr_debug("%s: #%d\n", __func__, p);
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pin = &pin_group->pins[p];
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err = stmp3xxx_request_pin(pin->id, pin->fun, label);
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if (err)
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goto out_err;
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stmp3xxx_pin_strength(pin->id, pin->strength, label);
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stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
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stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
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}
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return 0;
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out_err:
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/* Release allocated pins in case of error */
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while (--p >= 0) {
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pr_debug("%s: releasing #%d\n", __func__, p);
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stmp3xxx_release_pin(pin_group->pins[p].id, label);
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}
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return err;
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}
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EXPORT_SYMBOL(stmp3xxx_request_pin_group);
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void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
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{
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struct pin_desc *pin;
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int p;
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for (p = 0; p < pin_group->nr_pins; p++) {
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pin = &pin_group->pins[p];
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stmp3xxx_release_pin(pin->id, label);
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}
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}
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EXPORT_SYMBOL(stmp3xxx_release_pin_group);
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static int stmp3xxx_irq_to_gpio(int irq,
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struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
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{
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struct stmp3xxx_pinmux_bank *pm;
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for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
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if (pm->virq <= irq && irq < pm->virq + 32) {
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*bank = pm;
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*gpio = irq - pm->virq;
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return 0;
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}
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return -ENOENT;
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}
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static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
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{
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struct stmp3xxx_pinmux_bank *pm;
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unsigned gpio;
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int l, p;
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stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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l = 0; p = 1; break;
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case IRQ_TYPE_EDGE_FALLING:
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l = 0; p = 0; break;
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case IRQ_TYPE_LEVEL_HIGH:
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l = 1; p = 1; break;
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case IRQ_TYPE_LEVEL_LOW:
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l = 1; p = 0; break;
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default:
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pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
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__func__, type);
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return -ENXIO;
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}
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if (l)
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stmp3xxx_setl(1 << gpio, pm->irqlevel);
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else
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stmp3xxx_clearl(1 << gpio, pm->irqlevel);
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if (p)
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stmp3xxx_setl(1 << gpio, pm->irqpolarity);
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else
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stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
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return 0;
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}
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static void stmp3xxx_pin_ack_irq(unsigned irq)
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{
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u32 stat;
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struct stmp3xxx_pinmux_bank *pm;
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unsigned gpio;
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stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
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stat = __raw_readl(pm->irqstat) & (1 << gpio);
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stmp3xxx_clearl(stat, pm->irqstat);
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}
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static void stmp3xxx_pin_mask_irq(unsigned irq)
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{
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struct stmp3xxx_pinmux_bank *pm;
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unsigned gpio;
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stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
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stmp3xxx_clearl(1 << gpio, pm->irqen);
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stmp3xxx_clearl(1 << gpio, pm->pin2irq);
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}
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static void stmp3xxx_pin_unmask_irq(unsigned irq)
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{
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struct stmp3xxx_pinmux_bank *pm;
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unsigned gpio;
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stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
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stmp3xxx_setl(1 << gpio, pm->irqen);
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stmp3xxx_setl(1 << gpio, pm->pin2irq);
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}
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static inline
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struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
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{
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return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
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}
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static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
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return pm->virq + offset;
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}
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static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
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unsigned v;
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v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
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return v ? 1 : 0;
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}
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static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
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{
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struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
|
|
|
if (v)
|
|
stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
|
|
else
|
|
stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
|
|
}
|
|
|
|
static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
|
|
{
|
|
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
|
|
|
stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
|
|
stmp3xxx_gpio_set(chip, offset, v);
|
|
return 0;
|
|
}
|
|
|
|
static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
|
|
|
|
stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
|
|
return 0;
|
|
}
|
|
|
|
static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
|
|
}
|
|
|
|
static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
stmp3xxx_release_pin(chip->base + offset, "gpio");
|
|
}
|
|
|
|
static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
|
|
{
|
|
struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq);
|
|
int gpio_irq = pm->virq;
|
|
u32 stat = __raw_readl(pm->irqstat);
|
|
|
|
while (stat) {
|
|
if (stat & 1)
|
|
irq_desc[gpio_irq].handle_irq(gpio_irq,
|
|
&irq_desc[gpio_irq]);
|
|
gpio_irq++;
|
|
stat >>= 1;
|
|
}
|
|
}
|
|
|
|
static struct irq_chip gpio_irq_chip = {
|
|
.ack = stmp3xxx_pin_ack_irq,
|
|
.mask = stmp3xxx_pin_mask_irq,
|
|
.unmask = stmp3xxx_pin_unmask_irq,
|
|
.set_type = stmp3xxx_set_irqtype,
|
|
};
|
|
|
|
int __init stmp3xxx_pinmux_init(int virtual_irq_start)
|
|
{
|
|
int b, r = 0;
|
|
struct stmp3xxx_pinmux_bank *pm;
|
|
int virq;
|
|
|
|
for (b = 0; b < 3; b++) {
|
|
/* only banks 0,1,2 are allowed to GPIO */
|
|
pm = pinmux_banks + b;
|
|
pm->chip.base = 32 * b;
|
|
pm->chip.ngpio = 32;
|
|
pm->chip.owner = THIS_MODULE;
|
|
pm->chip.can_sleep = 1;
|
|
pm->chip.exported = 1;
|
|
pm->chip.to_irq = stmp3xxx_gpio_to_irq;
|
|
pm->chip.direction_input = stmp3xxx_gpio_input;
|
|
pm->chip.direction_output = stmp3xxx_gpio_output;
|
|
pm->chip.get = stmp3xxx_gpio_get;
|
|
pm->chip.set = stmp3xxx_gpio_set;
|
|
pm->chip.request = stmp3xxx_gpio_request;
|
|
pm->chip.free = stmp3xxx_gpio_free;
|
|
pm->virq = virtual_irq_start + b * 32;
|
|
|
|
for (virq = pm->virq; virq < pm->virq; virq++) {
|
|
gpio_irq_chip.mask(virq);
|
|
set_irq_chip(virq, &gpio_irq_chip);
|
|
set_irq_handler(virq, handle_level_irq);
|
|
set_irq_flags(virq, IRQF_VALID);
|
|
}
|
|
r = gpiochip_add(&pm->chip);
|
|
if (r < 0)
|
|
break;
|
|
set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq);
|
|
set_irq_data(pm->irq, pm);
|
|
}
|
|
return r;
|
|
}
|
|
|
|
MODULE_AUTHOR("Vladislav Buzov");
|
|
MODULE_LICENSE("GPL");
|