c7d3555ac0
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/*
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* fixup-loongson3.c
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*
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* Copyright (C) 2012 Lemote, Inc.
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* Author: Xiang Yu, xiangy@lemote.com
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* Chen Huacai, chenhc@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/pci.h>
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#include <boot_param.h>
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static void print_fixup_info(const struct pci_dev *pdev)
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{
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dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
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pdev->vendor, pdev->device, pdev->irq);
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}
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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print_fixup_info(dev);
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return dev->irq;
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}
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static void pci_fixup_radeon(struct pci_dev *pdev)
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{
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if (pdev->resource[PCI_ROM_RESOURCE].start)
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return;
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if (!loongson_sysconf.vgabios_addr)
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return;
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pdev->resource[PCI_ROM_RESOURCE].start =
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loongson_sysconf.vgabios_addr;
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pdev->resource[PCI_ROM_RESOURCE].end =
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loongson_sysconf.vgabios_addr + 256*1024 - 1;
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pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_COPY;
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dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
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PCI_ROM_RESOURCE, &pdev->resource[PCI_ROM_RESOURCE]);
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}
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
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PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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