c7d3555ac0
Loongson family machines use Hyper-Transport bus for inter-core connection and device connection. The PCI bus is a subordinate linked at HT1. With LEFI firmware interface, We don't need fixup for PCI irq routing (except providing a VBIOS of the integrated GPU). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6633 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/mips-boards/bonito64.h>
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#include <loongson.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#define HT1LO_PCICFG_BASE 0x1a000000
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#define HT1LO_PCICFG_BASE_TP1 0x1b000000
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static int loongson3_pci_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn,
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int where, u32 *data)
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{
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unsigned char busnum = bus->number;
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u_int64_t addr, type;
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void *addrp;
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int device = PCI_SLOT(devfn);
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int function = PCI_FUNC(devfn);
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int reg = where & ~3;
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addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
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if (busnum == 0) {
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if (device > 31)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE) | (addr & 0xffff));
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type = 0;
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} else {
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addrp = (void *)(TO_UNCAC(HT1LO_PCICFG_BASE_TP1) | (addr));
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type = 0x10000;
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}
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if (access_type == PCI_ACCESS_WRITE)
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writel(*data, addrp);
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else {
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*data = readl(addrp);
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if (*data == 0xffffffff) {
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*data = -1;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data = 0;
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int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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int ret;
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if (size == 4)
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data = val;
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else {
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ret = loongson3_pci_config_access(PCI_ACCESS_READ,
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bus, devfn, where, &data);
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if (ret != PCIBIOS_SUCCESSFUL)
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return ret;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
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bus, devfn, where, &data);
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return ret;
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}
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struct pci_ops loongson_pci_ops = {
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.read = loongson3_pci_pcibios_read,
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.write = loongson3_pci_pcibios_write
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};
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