c14af233fb
The original MIPS hibernate code flushes cache and TLB entries in
swsusp_arch_resume(). But they are removed in Commit 44eeab6741
(MIPS: Hibernation: Remove SMP TLB and cacheflushing code.). A cross-
CPU flush is surely unnecessary because all but the local CPU have
already been disabled. But a local flush (at least the TLB flush) is
needed. When we do hibernation on Loongson-3 with an E1000E NIC, it is
very easy to produce a kernel panic (kernel page fault, or unaligned
access). The root cause is E1000E driver use vzalloc_node() to allocate
pages, the stale TLB entries of the booting kernel will be misused by
the resumed target kernel.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/6643/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
63 lines
1.3 KiB
ArmAsm
63 lines
1.3 KiB
ArmAsm
/*
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* Hibernation support specific for mips - temporary page tables
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*
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* Licensed under the GPLv2
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*
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* Copyright (C) 2009 Lemote Inc.
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* Author: Hu Hongbing <huhb@lemote.com>
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* Wu Zhangjin <wuzhangjin@gmail.com>
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*/
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#include <asm/asm.h>
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.text
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LEAF(swsusp_arch_suspend)
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PTR_LA t0, saved_regs
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PTR_S ra, PT_R31(t0)
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PTR_S sp, PT_R29(t0)
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PTR_S fp, PT_R30(t0)
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PTR_S gp, PT_R28(t0)
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PTR_S s0, PT_R16(t0)
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PTR_S s1, PT_R17(t0)
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PTR_S s2, PT_R18(t0)
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PTR_S s3, PT_R19(t0)
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PTR_S s4, PT_R20(t0)
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PTR_S s5, PT_R21(t0)
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PTR_S s6, PT_R22(t0)
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PTR_S s7, PT_R23(t0)
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j swsusp_save
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END(swsusp_arch_suspend)
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LEAF(swsusp_arch_resume)
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PTR_L t0, restore_pblist
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0:
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PTR_L t1, PBE_ADDRESS(t0) /* source */
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PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
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PTR_ADDU t3, t1, _PAGE_SIZE
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1:
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REG_L t8, (t1)
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REG_S t8, (t2)
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PTR_ADDIU t1, t1, SZREG
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PTR_ADDIU t2, t2, SZREG
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bne t1, t3, 1b
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PTR_L t0, PBE_NEXT(t0)
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bnez t0, 0b
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jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
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PTR_LA t0, saved_regs
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PTR_L ra, PT_R31(t0)
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PTR_L sp, PT_R29(t0)
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PTR_L fp, PT_R30(t0)
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PTR_L gp, PT_R28(t0)
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PTR_L s0, PT_R16(t0)
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PTR_L s1, PT_R17(t0)
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PTR_L s2, PT_R18(t0)
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PTR_L s3, PT_R19(t0)
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PTR_L s4, PT_R20(t0)
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PTR_L s5, PT_R21(t0)
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PTR_L s6, PT_R22(t0)
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PTR_L s7, PT_R23(t0)
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PTR_LI v0, 0x0
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jr ra
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END(swsusp_arch_resume)
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