cc4f6944d0
Dynamic Frequency switch is a feature of clock controller by which request from peripherals allows automatic switching frequency of input clock without SW intervention. There are various performance levels associated with a root clock. When the input performance state changes, the source clocks and division ratios of the new performance state are loaded on to RCG via HW and the RCG switches to new clock frequency when the RCG is in DFS HW enabled mode. Register the root clock generators(RCG) to switch to use the dfs clock ops in the cases where DFS is enabled. The clk_round_rate() called by the clock consumer would invoke the dfs determine clock ops and would read the DFS performance level registers to identify all the frequencies supported and update the frequency table. The DFS clock consumers would maintain these frequency mapping and request the desired performance levels. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Rework registration logic to stop copying, change recalc_rate() to index directly into the table if possible and fallback to calculating on the fly with an assumed correct parent] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
178 lines
4.2 KiB
C
178 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */
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#ifndef __QCOM_CLK_RCG_H__
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#define __QCOM_CLK_RCG_H__
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
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struct freq_tbl {
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unsigned long freq;
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u8 src;
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u8 pre_div;
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u16 m;
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u16 n;
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};
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/**
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* struct mn - M/N:D counter
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* @mnctr_en_bit: bit to enable mn counter
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* @mnctr_reset_bit: bit to assert mn counter reset
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* @mnctr_mode_shift: lowest bit of mn counter mode field
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* @n_val_shift: lowest bit of n value field
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* @m_val_shift: lowest bit of m value field
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* @width: number of bits in m/n/d values
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* @reset_in_cc: true if the mnctr_reset_bit is in the CC register
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*/
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struct mn {
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u8 mnctr_en_bit;
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u8 mnctr_reset_bit;
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u8 mnctr_mode_shift;
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#define MNCTR_MODE_DUAL 0x2
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#define MNCTR_MODE_MASK 0x3
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u8 n_val_shift;
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u8 m_val_shift;
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u8 width;
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bool reset_in_cc;
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};
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/**
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* struct pre_div - pre-divider
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* @pre_div_shift: lowest bit of pre divider field
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* @pre_div_width: number of bits in predivider
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*/
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struct pre_div {
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u8 pre_div_shift;
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u8 pre_div_width;
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};
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/**
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* struct src_sel - source selector
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* @src_sel_shift: lowest bit of source selection field
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* @parent_map: map from software's parent index to hardware's src_sel field
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*/
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struct src_sel {
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u8 src_sel_shift;
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#define SRC_SEL_MASK 0x7
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const struct parent_map *parent_map;
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};
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/**
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* struct clk_rcg - root clock generator
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*
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* @ns_reg: NS register
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* @md_reg: MD register
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* @mn: mn counter
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* @p: pre divider
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* @s: source selector
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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* @lock: register lock
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*
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*/
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struct clk_rcg {
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u32 ns_reg;
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u32 md_reg;
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struct mn mn;
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struct pre_div p;
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struct src_sel s;
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_rcg_ops;
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extern const struct clk_ops clk_rcg_bypass_ops;
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extern const struct clk_ops clk_rcg_bypass2_ops;
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extern const struct clk_ops clk_rcg_pixel_ops;
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extern const struct clk_ops clk_rcg_esc_ops;
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extern const struct clk_ops clk_rcg_lcc_ops;
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#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
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/**
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* struct clk_dyn_rcg - root clock generator with glitch free mux
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*
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* @mux_sel_bit: bit to switch glitch free mux
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* @ns_reg: NS0 and NS1 register
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* @md_reg: MD0 and MD1 register
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* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
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* @mn: mn counter (banked)
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* @s: source selector (banked)
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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* @lock: register lock
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*
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*/
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struct clk_dyn_rcg {
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u32 ns_reg[2];
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u32 md_reg[2];
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u32 bank_reg;
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u8 mux_sel_bit;
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struct mn mn[2];
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struct pre_div p[2];
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struct src_sel s[2];
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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extern const struct clk_ops clk_dyn_rcg_ops;
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#define to_clk_dyn_rcg(_hw) \
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container_of(to_clk_regmap(_hw), struct clk_dyn_rcg, clkr)
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/**
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* struct clk_rcg2 - root clock generator
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*
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* @cmd_rcgr: corresponds to *_CMD_RCGR
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* @mnd_width: number of bits in m/n/d values
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* @hid_width: number of bits in half integer divider
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* @safe_src_index: safe src index value
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* @parent_map: map from software's parent index to hardware's src_sel field
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* @freq_tbl: frequency table
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* @clkr: regmap clock handle
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*
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*/
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struct clk_rcg2 {
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u32 cmd_rcgr;
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u8 mnd_width;
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u8 hid_width;
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u8 safe_src_index;
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const struct parent_map *parent_map;
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const struct freq_tbl *freq_tbl;
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struct clk_regmap clkr;
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};
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#define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
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extern const struct clk_ops clk_rcg2_ops;
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extern const struct clk_ops clk_rcg2_floor_ops;
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extern const struct clk_ops clk_edp_pixel_ops;
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extern const struct clk_ops clk_byte_ops;
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extern const struct clk_ops clk_byte2_ops;
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extern const struct clk_ops clk_pixel_ops;
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extern const struct clk_ops clk_gfx3d_ops;
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extern const struct clk_ops clk_rcg2_shared_ops;
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struct clk_rcg_dfs_data {
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struct clk_rcg2 *rcg;
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struct clk_init_data *init;
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};
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#define DEFINE_RCG_DFS(r) \
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{ .rcg = &r##_src, .init = &r##_init }
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extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,
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const struct clk_rcg_dfs_data *rcgs,
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size_t len);
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#endif
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