633e79650b
Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
29 lines
996 B
Makefile
29 lines
996 B
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
obj-y += clk.o
|
|
obj-y += clk-audio-sync.o
|
|
obj-y += clk-dfll.o
|
|
obj-y += clk-divider.o
|
|
obj-y += clk-periph.o
|
|
obj-y += clk-periph-fixed.o
|
|
obj-y += clk-periph-gate.o
|
|
obj-y += clk-pll.o
|
|
obj-y += clk-pll-out.o
|
|
obj-y += clk-sdmmc-mux.o
|
|
obj-y += clk-super.o
|
|
obj-y += clk-tegra-audio.o
|
|
obj-y += clk-tegra-periph.o
|
|
obj-y += clk-tegra-pmc.o
|
|
obj-y += clk-tegra-fixed.o
|
|
obj-y += clk-tegra-super-gen4.o
|
|
obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o
|
|
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
|
|
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
|
|
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o
|
|
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o
|
|
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124-dfll-fcpu.o
|
|
obj-$(CONFIG_ARCH_TEGRA_132_SOC) += clk-tegra124.o
|
|
obj-y += cvb.o
|
|
obj-$(CONFIG_ARCH_TEGRA_210_SOC) += clk-tegra210.o
|
|
obj-$(CONFIG_CLK_TEGRA_BPMP) += clk-bpmp.o
|
|
obj-y += clk-utils.o
|