Andrew Waterman f1b65f20fb RISC-V: Limit the scope of TLB shootdowns ... RISC-V systems perform TLB shootdows via the SBI, which currently performs an IPI to each of the remote harts which then performs a local TLB flush. This process is a bit on the slow side, but we can at least speed it up for some common cases by restricting the set of harts to shoot down to the actual set of harts that are currently participating in the given mm context, as opposed to the entire system. This should provide a measurable performance increase, but we haven't measured it. Regardless, it seems like obviously the right thing to do here. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>		2018-01-30 19:13:33 -08:00
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configs	RISC-V: Add a basic defconfig	2018-01-07 15:14:36 -08:00
include	RISC-V: Limit the scope of TLB shootdowns	2018-01-30 19:13:33 -08:00
kernel	riscv: disable SUM in the exception handler	2018-01-30 19:12:38 -08:00
lib	RISC-V: Export some expected symbols for modules	2017-11-30 10:01:10 -08:00
mm	riscv: rename SR_* constants to match the spec	2018-01-07 15:14:39 -08:00
Kconfig	riscv/ftrace: Add basic support	2018-01-30 19:10:54 -08:00
Makefile	RISC-V: Build Infrastructure	2017-09-26 15:26:49 -07:00