f1f0366dd6
Calculate and save the timing parameters that need to be programmed if we need to enable L1.2 substates later. We use the same logic (and a constant value for 1 of the parameters) as used by Intel's coreboot: https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html https://review.coreboot.org/#/c/8832/ Signed-off-by: Rajat Jain <rajatja@google.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
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| .. | ||
| aer | ||
| aspm.c | ||
| Kconfig | ||
| Makefile | ||
| pcie-dpc.c | ||
| pme.c | ||
| portdrv.h | ||
| portdrv_acpi.c | ||
| portdrv_bus.c | ||
| portdrv_core.c | ||
| portdrv_pci.c | ||
| ptm.c | ||