![Fenghua Yu](/assets/img/avatar_default.png)
Define struct rdt_resource to hold all the parameterized values for an RDT resource and fill in the CPUID enumerated values from leaf 0x10 if available. Hard code them for the MSR detected Haswells. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com> Cc: "Tony Luck" <tony.luck@intel.com> Cc: "David Carrillo-Cisneros" <davidcc@google.com> Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com> Cc: "Peter Zijlstra" <peterz@infradead.org> Cc: "Stephane Eranian" <eranian@google.com> Cc: "Dave Hansen" <dave.hansen@intel.com> Cc: "Shaohua Li" <shli@fb.com> Cc: "Nilay Vaish" <nilayvaish@gmail.com> Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com> Cc: "Ingo Molnar" <mingo@elte.hu> Cc: "Borislav Petkov" <bp@suse.de> Cc: "H. Peter Anvin" <h.peter.anvin@intel.com> Link: http://lkml.kernel.org/r/1477142405-32078-9-git-send-email-fenghua.yu@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
193 lines
5 KiB
C
193 lines
5 KiB
C
/*
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* Resource Director Technology(RDT)
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* - Cache Allocation code.
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*
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* Copyright (C) 2016 Intel Corporation
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*
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* Authors:
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* Fenghua Yu <fenghua.yu@intel.com>
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* Tony Luck <tony.luck@intel.com>
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* Vikas Shivappa <vikas.shivappa@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* More information about RDT be found in the Intel (R) x86 Architecture
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* Software Developer Manual June 2016, volume 3, section 17.17.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <asm/intel_rdt_common.h>
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#include <asm/intel-family.h>
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#include <asm/intel_rdt.h>
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#define domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].domains)
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struct rdt_resource rdt_resources_all[] = {
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{
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.name = "L3",
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.domains = domain_init(RDT_RESOURCE_L3),
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.msr_base = IA32_L3_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 3,
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.cbm_idx_multi = 1,
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.cbm_idx_offset = 0
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},
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{
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.name = "L3DATA",
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.domains = domain_init(RDT_RESOURCE_L3DATA),
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.msr_base = IA32_L3_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 3,
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.cbm_idx_multi = 2,
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.cbm_idx_offset = 0
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},
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{
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.name = "L3CODE",
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.domains = domain_init(RDT_RESOURCE_L3CODE),
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.msr_base = IA32_L3_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 3,
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.cbm_idx_multi = 2,
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.cbm_idx_offset = 1
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},
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{
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.name = "L2",
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.domains = domain_init(RDT_RESOURCE_L2),
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.msr_base = IA32_L2_CBM_BASE,
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.min_cbm_bits = 1,
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.cache_level = 2,
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.cbm_idx_multi = 1,
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.cbm_idx_offset = 0
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},
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};
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/*
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* cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
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* as they do not have CPUID enumeration support for Cache allocation.
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* The check for Vendor/Family/Model is not enough to guarantee that
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* the MSRs won't #GP fault because only the following SKUs support
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* CAT:
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* Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz
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* Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz
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* Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz
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* Intel(R) Xeon(R) CPU E5-2618L v3 @ 2.30GHz
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* Intel(R) Xeon(R) CPU E5-2608L v3 @ 2.00GHz
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* Intel(R) Xeon(R) CPU E5-2658A v3 @ 2.20GHz
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*
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* Probe by trying to write the first of the L3 cach mask registers
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* and checking that the bits stick. Max CLOSids is always 4 and max cbm length
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* is always 20 on hsw server parts. The minimum cache bitmask length
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* allowed for HSW server is always 2 bits. Hardcode all of them.
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*/
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static inline bool cache_alloc_hsw_probe(void)
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{
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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boot_cpu_data.x86 == 6 &&
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boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X) {
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struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3];
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u32 l, h, max_cbm = BIT_MASK(20) - 1;
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if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
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return false;
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rdmsr(IA32_L3_CBM_BASE, l, h);
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/* If all the bits were set in MSR, return success */
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if (l != max_cbm)
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return false;
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r->num_closid = 4;
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r->cbm_len = 20;
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r->max_cbm = max_cbm;
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r->min_cbm_bits = 2;
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r->capable = true;
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r->enabled = true;
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return true;
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}
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return false;
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}
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static void rdt_get_config(int idx, struct rdt_resource *r)
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{
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union cpuid_0x10_1_eax eax;
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union cpuid_0x10_1_edx edx;
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u32 ebx, ecx;
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cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full);
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r->num_closid = edx.split.cos_max + 1;
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r->cbm_len = eax.split.cbm_len + 1;
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r->max_cbm = BIT_MASK(eax.split.cbm_len + 1) - 1;
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r->capable = true;
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r->enabled = true;
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}
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static void rdt_get_cdp_l3_config(int type)
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{
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struct rdt_resource *r_l3 = &rdt_resources_all[RDT_RESOURCE_L3];
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struct rdt_resource *r = &rdt_resources_all[type];
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r->num_closid = r_l3->num_closid / 2;
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r->cbm_len = r_l3->cbm_len;
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r->max_cbm = r_l3->max_cbm;
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r->capable = true;
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/*
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* By default, CDP is disabled. CDP can be enabled by mount parameter
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* "cdp" during resctrl file system mount time.
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*/
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r->enabled = false;
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}
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static inline bool get_rdt_resources(void)
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{
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bool ret = false;
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if (cache_alloc_hsw_probe())
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return true;
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if (!boot_cpu_has(X86_FEATURE_RDT_A))
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return false;
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if (boot_cpu_has(X86_FEATURE_CAT_L3)) {
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rdt_get_config(1, &rdt_resources_all[RDT_RESOURCE_L3]);
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if (boot_cpu_has(X86_FEATURE_CDP_L3)) {
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rdt_get_cdp_l3_config(RDT_RESOURCE_L3DATA);
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rdt_get_cdp_l3_config(RDT_RESOURCE_L3CODE);
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}
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ret = true;
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}
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if (boot_cpu_has(X86_FEATURE_CAT_L2)) {
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/* CPUID 0x10.2 fields are same format at 0x10.1 */
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rdt_get_config(2, &rdt_resources_all[RDT_RESOURCE_L2]);
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ret = true;
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}
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return ret;
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}
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static int __init intel_rdt_late_init(void)
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{
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struct rdt_resource *r;
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if (!get_rdt_resources())
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return -ENODEV;
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for_each_capable_rdt_resource(r)
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pr_info("Intel RDT %s allocation detected\n", r->name);
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return 0;
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}
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late_initcall(intel_rdt_late_init);
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