![Chris Wilson](/assets/img/avatar_default.png)
Ignoring the legacy DRI1 code, and a couple of special cases (to be discussed later), all access to the ring is mediated through requests. The first write to a ring will grab a seqno and mark the ring as having an outstanding_lazy_request. Either through explicitly adding a request after an execbuffer or through an implicit wait (either by the CPU or by a semaphore), that sequence of writes will be terminated with a request. So we can ellide all the intervening writes to the tail register and send the entire command stream to the GPU at once. This will reduce the number of *serialising* writes to the tail register by a factor or 3-5 times (depending upon architecture and number of workarounds, context switches, etc involved). This becomes even more noticeable when the register write is overloaded with a number of debugging tools. The astute reader will wonder if it is then possible to overflow the ring with a single command. It is not. When we start a command sequence to the ring, we check for available space and issue a wait in case we have not. The ring wait will in this case be forced to flush the outstanding register write and then poll the ACTHD for sufficient space to continue. The exception to the rule where everything is inside a request are a few initialisation cases where we may want to write GPU commands via the CS before userspace wakes up and page flips. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
282 lines
8 KiB
C
282 lines
8 KiB
C
#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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/*
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* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
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* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
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* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
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*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
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* cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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#define I915_RING_FREE_SPACE 64
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struct intel_hw_status_page {
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u32 *page_addr;
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unsigned int gfx_addr;
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struct drm_i915_gem_object *obj;
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};
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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enum intel_ring_hangcheck_action {
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HANGCHECK_IDLE = 0,
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HANGCHECK_WAIT,
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HANGCHECK_ACTIVE,
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HANGCHECK_KICK,
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HANGCHECK_HUNG,
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};
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struct intel_ring_hangcheck {
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bool deadlock;
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u32 seqno;
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u32 acthd;
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int score;
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enum intel_ring_hangcheck_action action;
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};
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struct intel_ring_buffer {
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const char *name;
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enum intel_ring_id {
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RCS = 0x0,
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VCS,
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BCS,
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VECS,
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} id;
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#define I915_NUM_RINGS 4
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u32 mmio_base;
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void __iomem *virtual_start;
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struct drm_device *dev;
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struct drm_i915_gem_object *obj;
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u32 head;
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u32 tail;
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int space;
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int size;
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int effective_size;
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struct intel_hw_status_page status_page;
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/** We track the position of the requests in the ring buffer, and
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* when each is retired we increment last_retired_head as the GPU
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* must have finished processing the request and so we know we
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* can advance the ringbuffer up to that position.
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*
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* last_retired_head is set to -1 after the value is consumed so
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* we can detect new retirements.
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*/
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u32 last_retired_head;
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unsigned irq_refcount; /* protected by dev_priv->irq_lock */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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u32 trace_irq_seqno;
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u32 sync_seqno[I915_NUM_RINGS-1];
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bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
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void (*irq_put)(struct intel_ring_buffer *ring);
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int (*init)(struct intel_ring_buffer *ring);
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void (*write_tail)(struct intel_ring_buffer *ring,
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u32 value);
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int __must_check (*flush)(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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int (*add_request)(struct intel_ring_buffer *ring);
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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u32 (*get_seqno)(struct intel_ring_buffer *ring,
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bool lazy_coherency);
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void (*set_seqno)(struct intel_ring_buffer *ring,
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u32 seqno);
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int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
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u32 offset, u32 length,
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unsigned flags);
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#define I915_DISPATCH_SECURE 0x1
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#define I915_DISPATCH_PINNED 0x2
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void (*cleanup)(struct intel_ring_buffer *ring);
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int (*sync_to)(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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u32 seqno);
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/* our mbox written by others */
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u32 semaphore_register[I915_NUM_RINGS];
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/* mboxes this ring signals to */
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u32 signal_mbox[I915_NUM_RINGS];
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_rendering_seqno
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* List of breadcrumbs associated with GPU requests currently
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* outstanding.
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*/
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struct list_head request_list;
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/**
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* Do we have some not yet emitted requests outstanding?
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*/
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struct drm_i915_gem_request *preallocated_lazy_request;
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u32 outstanding_lazy_seqno;
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bool gpu_caches_dirty;
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bool fbc_dirty;
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wait_queue_head_t irq_queue;
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/**
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* Do an explicit TLB flush before MI_SET_CONTEXT
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*/
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bool itlb_before_ctx_switch;
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struct i915_hw_context *default_context;
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struct i915_hw_context *last_context;
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struct intel_ring_hangcheck hangcheck;
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struct {
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struct drm_i915_gem_object *obj;
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u32 gtt_offset;
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volatile u32 *cpu_page;
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} scratch;
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};
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static inline bool
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intel_ring_initialized(struct intel_ring_buffer *ring)
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{
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return ring->obj != NULL;
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}
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static inline unsigned
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intel_ring_flag(struct intel_ring_buffer *ring)
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{
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return 1 << ring->id;
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}
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static inline u32
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intel_ring_sync_index(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *other)
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{
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int idx;
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/*
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* cs -> 0 = vcs, 1 = bcs
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* vcs -> 0 = bcs, 1 = cs,
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* bcs -> 0 = cs, 1 = vcs.
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*/
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idx = (other - ring) - 1;
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if (idx < 0)
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idx += I915_NUM_RINGS;
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return idx;
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}
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static inline u32
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intel_read_status_page(struct intel_ring_buffer *ring,
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int reg)
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{
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/* Ensure that the compiler doesn't optimize away the load. */
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barrier();
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return ring->status_page.page_addr[reg];
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}
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static inline void
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intel_write_status_page(struct intel_ring_buffer *ring,
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int reg, u32 value)
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{
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ring->status_page.page_addr[reg] = value;
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}
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/**
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* Reads a dword out of the status page, which is written to from the command
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* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
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* MI_STORE_DATA_IMM.
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*
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* The following dwords have a reserved meaning:
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* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
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* 0x04: ring 0 head pointer
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* 0x05: ring 1 head pointer (915-class)
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* 0x06: ring 2 head pointer (915-class)
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* 0x10-0x1b: Context status DWords (GM45)
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* 0x1f: Last written status offset. (GM45)
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*
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* The area from dword 0x20 to 0x3ff is available for driver usage.
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*/
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#define I915_GEM_HWS_INDEX 0x20
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#define I915_GEM_HWS_SCRATCH_INDEX 0x30
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#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
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void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
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int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
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static inline void intel_ring_emit(struct intel_ring_buffer *ring,
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u32 data)
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{
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iowrite32(data, ring->virtual_start + ring->tail);
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ring->tail += 4;
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}
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static inline void intel_ring_advance(struct intel_ring_buffer *ring)
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{
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ring->tail &= ring->size - 1;
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}
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void __intel_ring_advance(struct intel_ring_buffer *ring);
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int __must_check intel_ring_idle(struct intel_ring_buffer *ring);
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void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno);
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int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
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int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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int intel_init_vebox_ring_buffer(struct drm_device *dev);
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
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void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
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static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
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{
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return ring->tail;
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}
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static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring)
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{
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BUG_ON(ring->outstanding_lazy_seqno == 0);
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return ring->outstanding_lazy_seqno;
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}
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static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
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{
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if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
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ring->trace_irq_seqno = seqno;
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}
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/* DRI warts */
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int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
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#endif /* _INTEL_RINGBUFFER_H_ */
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