![Tejun Heo](/assets/img/avatar_default.png)
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
812 lines
24 KiB
C
812 lines
24 KiB
C
/*======================================================================
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Device driver for Databook TCIC-2 PCMCIA controller
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tcic.c 1.111 2000/02/15 04:13:12
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The contents of this file are subject to the Mozilla Public
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License Version 1.1 (the "License"); you may not use this file
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except in compliance with the License. You may obtain a copy of
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the License at http://www.mozilla.org/MPL/
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Software distributed under the License is distributed on an "AS
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IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
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implied. See the License for the specific language governing
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rights and limitations under the License.
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The initial developer of the original code is David A. Hinds
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<dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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Alternatively, the contents of this file may be used under the
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terms of the GNU General Public License version 2 (the "GPL"), in which
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case the provisions of the GPL are applicable instead of the
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above. If you wish to allow the use of your version of this file
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only under the terms of the GPL and not to allow others to use
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your version of this file under the MPL, indicate your decision
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by deleting the provisions above and replace them with the notice
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and other provisions required by the GPL. If you do not delete
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the provisions above, a recipient may use your version of this
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file under either the MPL or the GPL.
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======================================================================*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/fcntl.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/platform_device.h>
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#include <linux/bitops.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <pcmcia/cs_types.h>
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#include <pcmcia/cs.h>
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#include <pcmcia/ss.h>
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#include "tcic.h"
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MODULE_AUTHOR("David Hinds <dahinds@users.sourceforge.net>");
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MODULE_DESCRIPTION("Databook TCIC-2 PCMCIA socket driver");
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MODULE_LICENSE("Dual MPL/GPL");
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/*====================================================================*/
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/* Parameters that can be set with 'insmod' */
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/* The base port address of the TCIC-2 chip */
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static unsigned long tcic_base = TCIC_BASE;
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/* Specify a socket number to ignore */
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static int ignore = -1;
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/* Probe for safe interrupts? */
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static int do_scan = 1;
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/* Bit map of interrupts to choose from */
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static u_int irq_mask = 0xffff;
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static int irq_list[16];
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static unsigned int irq_list_count;
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/* The card status change interrupt -- 0 means autoselect */
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static int cs_irq;
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/* Poll status interval -- 0 means default to interrupt */
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static int poll_interval;
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/* Delay for card status double-checking */
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static int poll_quick = HZ/20;
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/* CCLK external clock time, in nanoseconds. 70 ns = 14.31818 MHz */
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static int cycle_time = 70;
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module_param(tcic_base, ulong, 0444);
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module_param(ignore, int, 0444);
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module_param(do_scan, int, 0444);
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module_param(irq_mask, int, 0444);
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module_param_array(irq_list, int, &irq_list_count, 0444);
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module_param(cs_irq, int, 0444);
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module_param(poll_interval, int, 0444);
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module_param(poll_quick, int, 0444);
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module_param(cycle_time, int, 0444);
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/*====================================================================*/
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static irqreturn_t tcic_interrupt(int irq, void *dev);
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static void tcic_timer(u_long data);
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static struct pccard_operations tcic_operations;
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struct tcic_socket {
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u_short psock;
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u_char last_sstat;
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u_char id;
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struct pcmcia_socket socket;
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};
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static struct timer_list poll_timer;
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static int tcic_timer_pending;
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static int sockets;
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static struct tcic_socket socket_table[2];
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/*====================================================================*/
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/* Trick when selecting interrupts: the TCIC sktirq pin is supposed
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to map to irq 11, but is coded as 0 or 1 in the irq registers. */
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#define TCIC_IRQ(x) ((x) ? (((x) == 11) ? 1 : (x)) : 15)
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#ifdef DEBUG_X
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static u_char tcic_getb(u_char reg)
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{
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u_char val = inb(tcic_base+reg);
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printk(KERN_DEBUG "tcic_getb(%#lx) = %#x\n", tcic_base+reg, val);
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return val;
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}
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static u_short tcic_getw(u_char reg)
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{
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u_short val = inw(tcic_base+reg);
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printk(KERN_DEBUG "tcic_getw(%#lx) = %#x\n", tcic_base+reg, val);
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return val;
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}
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static void tcic_setb(u_char reg, u_char data)
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{
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printk(KERN_DEBUG "tcic_setb(%#lx, %#x)\n", tcic_base+reg, data);
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outb(data, tcic_base+reg);
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}
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static void tcic_setw(u_char reg, u_short data)
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{
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printk(KERN_DEBUG "tcic_setw(%#lx, %#x)\n", tcic_base+reg, data);
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outw(data, tcic_base+reg);
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}
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#else
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#define tcic_getb(reg) inb(tcic_base+reg)
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#define tcic_getw(reg) inw(tcic_base+reg)
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#define tcic_setb(reg, data) outb(data, tcic_base+reg)
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#define tcic_setw(reg, data) outw(data, tcic_base+reg)
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#endif
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static void tcic_setl(u_char reg, u_int data)
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{
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#ifdef DEBUG_X
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printk(KERN_DEBUG "tcic_setl(%#x, %#lx)\n", tcic_base+reg, data);
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#endif
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outw(data & 0xffff, tcic_base+reg);
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outw(data >> 16, tcic_base+reg+2);
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}
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static void tcic_aux_setb(u_short reg, u_char data)
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{
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u_char mode = (tcic_getb(TCIC_MODE) & TCIC_MODE_PGMMASK) | reg;
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tcic_setb(TCIC_MODE, mode);
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tcic_setb(TCIC_AUX, data);
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}
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static u_short tcic_aux_getw(u_short reg)
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{
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u_char mode = (tcic_getb(TCIC_MODE) & TCIC_MODE_PGMMASK) | reg;
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tcic_setb(TCIC_MODE, mode);
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return tcic_getw(TCIC_AUX);
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}
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static void tcic_aux_setw(u_short reg, u_short data)
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{
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u_char mode = (tcic_getb(TCIC_MODE) & TCIC_MODE_PGMMASK) | reg;
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tcic_setb(TCIC_MODE, mode);
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tcic_setw(TCIC_AUX, data);
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}
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/*====================================================================*/
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/* Time conversion functions */
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static int to_cycles(int ns)
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{
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if (ns < 14)
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return 0;
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else
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return 2*(ns-14)/cycle_time;
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}
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/*====================================================================*/
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static volatile u_int irq_hits;
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static irqreturn_t __init tcic_irq_count(int irq, void *dev)
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{
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irq_hits++;
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return IRQ_HANDLED;
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}
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static u_int __init try_irq(int irq)
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{
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u_short cfg;
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irq_hits = 0;
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if (request_irq(irq, tcic_irq_count, 0, "irq scan", tcic_irq_count) != 0)
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return -1;
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mdelay(10);
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if (irq_hits) {
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free_irq(irq, tcic_irq_count);
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return -1;
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}
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/* Generate one interrupt */
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cfg = TCIC_SYSCFG_AUTOBUSY | 0x0a00;
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tcic_aux_setw(TCIC_AUX_SYSCFG, cfg | TCIC_IRQ(irq));
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tcic_setb(TCIC_IENA, TCIC_IENA_ERR | TCIC_IENA_CFG_HIGH);
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tcic_setb(TCIC_ICSR, TCIC_ICSR_ERR | TCIC_ICSR_JAM);
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udelay(1000);
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free_irq(irq, tcic_irq_count);
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/* Turn off interrupts */
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tcic_setb(TCIC_IENA, TCIC_IENA_CFG_OFF);
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while (tcic_getb(TCIC_ICSR))
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tcic_setb(TCIC_ICSR, TCIC_ICSR_JAM);
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tcic_aux_setw(TCIC_AUX_SYSCFG, cfg);
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return (irq_hits != 1);
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}
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static u_int __init irq_scan(u_int mask0)
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{
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u_int mask1;
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int i;
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#ifdef __alpha__
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#define PIC 0x4d0
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/* Don't probe level-triggered interrupts -- reserved for PCI */
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int level_mask = inb_p(PIC) | (inb_p(PIC+1) << 8);
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if (level_mask)
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mask0 &= ~level_mask;
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#endif
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mask1 = 0;
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if (do_scan) {
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for (i = 0; i < 16; i++)
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if ((mask0 & (1 << i)) && (try_irq(i) == 0))
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mask1 |= (1 << i);
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for (i = 0; i < 16; i++)
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if ((mask1 & (1 << i)) && (try_irq(i) != 0)) {
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mask1 ^= (1 << i);
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}
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}
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if (mask1) {
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printk("scanned");
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} else {
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/* Fallback: just find interrupts that aren't in use */
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for (i = 0; i < 16; i++)
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if ((mask0 & (1 << i)) &&
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(request_irq(i, tcic_irq_count, 0, "x", tcic_irq_count) == 0)) {
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mask1 |= (1 << i);
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free_irq(i, tcic_irq_count);
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}
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printk("default");
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}
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printk(") = ");
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for (i = 0; i < 16; i++)
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if (mask1 & (1<<i))
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printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i);
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printk(" ");
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return mask1;
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}
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/*======================================================================
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See if a card is present, powered up, in IO mode, and already
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bound to a (non-PCMCIA) Linux driver.
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We make an exception for cards that look like serial devices.
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======================================================================*/
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static int __init is_active(int s)
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{
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u_short scf1, ioctl, base, num;
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u_char pwr, sstat;
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u_int addr;
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tcic_setl(TCIC_ADDR, (s << TCIC_ADDR_SS_SHFT)
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| TCIC_ADDR_INDREG | TCIC_SCF1(s));
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scf1 = tcic_getw(TCIC_DATA);
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pwr = tcic_getb(TCIC_PWR);
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sstat = tcic_getb(TCIC_SSTAT);
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addr = TCIC_IWIN(s, 0);
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tcic_setw(TCIC_ADDR, addr + TCIC_IBASE_X);
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base = tcic_getw(TCIC_DATA);
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tcic_setw(TCIC_ADDR, addr + TCIC_ICTL_X);
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ioctl = tcic_getw(TCIC_DATA);
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if (ioctl & TCIC_ICTL_TINY)
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num = 1;
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else {
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num = (base ^ (base-1));
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base = base & (base-1);
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}
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if ((sstat & TCIC_SSTAT_CD) && (pwr & TCIC_PWR_VCC(s)) &&
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(scf1 & TCIC_SCF1_IOSTS) && (ioctl & TCIC_ICTL_ENA) &&
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((base & 0xfeef) != 0x02e8)) {
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struct resource *res = request_region(base, num, "tcic-2");
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if (!res) /* region is busy */
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return 1;
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release_region(base, num);
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}
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return 0;
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}
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/*======================================================================
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This returns the revision code for the specified socket.
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======================================================================*/
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static int __init get_tcic_id(void)
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{
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u_short id;
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tcic_aux_setw(TCIC_AUX_TEST, TCIC_TEST_DIAG);
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id = tcic_aux_getw(TCIC_AUX_ILOCK);
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id = (id & TCIC_ILOCKTEST_ID_MASK) >> TCIC_ILOCKTEST_ID_SH;
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tcic_aux_setw(TCIC_AUX_TEST, 0);
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return id;
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}
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/*====================================================================*/
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static struct platform_driver tcic_driver = {
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.driver = {
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.name = "tcic-pcmcia",
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.owner = THIS_MODULE,
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},
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};
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static struct platform_device tcic_device = {
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.name = "tcic-pcmcia",
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.id = 0,
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};
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static int __init init_tcic(void)
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{
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int i, sock, ret = 0;
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u_int mask, scan;
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if (platform_driver_register(&tcic_driver))
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return -1;
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printk(KERN_INFO "Databook TCIC-2 PCMCIA probe: ");
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sock = 0;
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if (!request_region(tcic_base, 16, "tcic-2")) {
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printk("could not allocate ports,\n ");
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platform_driver_unregister(&tcic_driver);
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return -ENODEV;
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}
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else {
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tcic_setw(TCIC_ADDR, 0);
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if (tcic_getw(TCIC_ADDR) == 0) {
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tcic_setw(TCIC_ADDR, 0xc3a5);
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if (tcic_getw(TCIC_ADDR) == 0xc3a5) sock = 2;
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}
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if (sock == 0) {
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/* See if resetting the controller does any good */
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tcic_setb(TCIC_SCTRL, TCIC_SCTRL_RESET);
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tcic_setb(TCIC_SCTRL, 0);
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tcic_setw(TCIC_ADDR, 0);
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if (tcic_getw(TCIC_ADDR) == 0) {
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tcic_setw(TCIC_ADDR, 0xc3a5);
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if (tcic_getw(TCIC_ADDR) == 0xc3a5) sock = 2;
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}
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}
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}
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if (sock == 0) {
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printk("not found.\n");
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release_region(tcic_base, 16);
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platform_driver_unregister(&tcic_driver);
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return -ENODEV;
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}
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sockets = 0;
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for (i = 0; i < sock; i++) {
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if ((i == ignore) || is_active(i)) continue;
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socket_table[sockets].psock = i;
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socket_table[sockets].id = get_tcic_id();
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socket_table[sockets].socket.owner = THIS_MODULE;
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/* only 16-bit cards, memory windows must be size-aligned */
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/* No PCI or CardBus support */
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socket_table[sockets].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN;
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/* irq 14, 11, 10, 7, 6, 5, 4, 3 */
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socket_table[sockets].socket.irq_mask = 0x4cf8;
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/* 4K minimum window size */
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socket_table[sockets].socket.map_size = 0x1000;
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sockets++;
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}
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switch (socket_table[0].id) {
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case TCIC_ID_DB86082:
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printk("DB86082"); break;
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case TCIC_ID_DB86082A:
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printk("DB86082A"); break;
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case TCIC_ID_DB86084:
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printk("DB86084"); break;
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case TCIC_ID_DB86084A:
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printk("DB86084A"); break;
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case TCIC_ID_DB86072:
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printk("DB86072"); break;
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case TCIC_ID_DB86184:
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printk("DB86184"); break;
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case TCIC_ID_DB86082B:
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printk("DB86082B"); break;
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default:
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printk("Unknown ID 0x%02x", socket_table[0].id);
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}
|
|
|
|
/* Set up polling */
|
|
poll_timer.function = &tcic_timer;
|
|
poll_timer.data = 0;
|
|
init_timer(&poll_timer);
|
|
|
|
/* Build interrupt mask */
|
|
printk(KERN_CONT ", %d sockets\n", sockets);
|
|
printk(KERN_INFO " irq list (");
|
|
if (irq_list_count == 0)
|
|
mask = irq_mask;
|
|
else
|
|
for (i = mask = 0; i < irq_list_count; i++)
|
|
mask |= (1<<irq_list[i]);
|
|
|
|
/* irq 14, 11, 10, 7, 6, 5, 4, 3 */
|
|
mask &= 0x4cf8;
|
|
/* Scan interrupts */
|
|
mask = irq_scan(mask);
|
|
for (i=0;i<sockets;i++)
|
|
socket_table[i].socket.irq_mask = mask;
|
|
|
|
/* Check for only two interrupts available */
|
|
scan = (mask & (mask-1));
|
|
if (((scan & (scan-1)) == 0) && (poll_interval == 0))
|
|
poll_interval = HZ;
|
|
|
|
if (poll_interval == 0) {
|
|
/* Avoid irq 12 unless it is explicitly requested */
|
|
u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12));
|
|
for (i = 15; i > 0; i--)
|
|
if ((cs_mask & (1 << i)) &&
|
|
(request_irq(i, tcic_interrupt, 0, "tcic",
|
|
tcic_interrupt) == 0))
|
|
break;
|
|
cs_irq = i;
|
|
if (cs_irq == 0) poll_interval = HZ;
|
|
}
|
|
|
|
if (socket_table[0].socket.irq_mask & (1 << 11))
|
|
printk("sktirq is irq 11, ");
|
|
if (cs_irq != 0)
|
|
printk("status change on irq %d\n", cs_irq);
|
|
else
|
|
printk("polled status, interval = %d ms\n",
|
|
poll_interval * 1000 / HZ);
|
|
|
|
for (i = 0; i < sockets; i++) {
|
|
tcic_setw(TCIC_ADDR+2, socket_table[i].psock << TCIC_SS_SHFT);
|
|
socket_table[i].last_sstat = tcic_getb(TCIC_SSTAT);
|
|
}
|
|
|
|
/* jump start interrupt handler, if needed */
|
|
tcic_interrupt(0, NULL);
|
|
|
|
platform_device_register(&tcic_device);
|
|
|
|
for (i = 0; i < sockets; i++) {
|
|
socket_table[i].socket.ops = &tcic_operations;
|
|
socket_table[i].socket.resource_ops = &pccard_nonstatic_ops;
|
|
socket_table[i].socket.dev.parent = &tcic_device.dev;
|
|
ret = pcmcia_register_socket(&socket_table[i].socket);
|
|
if (ret && i)
|
|
pcmcia_unregister_socket(&socket_table[0].socket);
|
|
}
|
|
|
|
return ret;
|
|
|
|
return 0;
|
|
|
|
} /* init_tcic */
|
|
|
|
/*====================================================================*/
|
|
|
|
static void __exit exit_tcic(void)
|
|
{
|
|
int i;
|
|
|
|
del_timer_sync(&poll_timer);
|
|
if (cs_irq != 0) {
|
|
tcic_aux_setw(TCIC_AUX_SYSCFG, TCIC_SYSCFG_AUTOBUSY|0x0a00);
|
|
free_irq(cs_irq, tcic_interrupt);
|
|
}
|
|
release_region(tcic_base, 16);
|
|
|
|
for (i = 0; i < sockets; i++) {
|
|
pcmcia_unregister_socket(&socket_table[i].socket);
|
|
}
|
|
|
|
platform_device_unregister(&tcic_device);
|
|
platform_driver_unregister(&tcic_driver);
|
|
} /* exit_tcic */
|
|
|
|
/*====================================================================*/
|
|
|
|
static irqreturn_t tcic_interrupt(int irq, void *dev)
|
|
{
|
|
int i, quick = 0;
|
|
u_char latch, sstat;
|
|
u_short psock;
|
|
u_int events;
|
|
static volatile int active = 0;
|
|
|
|
if (active) {
|
|
printk(KERN_NOTICE "tcic: reentered interrupt handler!\n");
|
|
return IRQ_NONE;
|
|
} else
|
|
active = 1;
|
|
|
|
pr_debug("tcic_interrupt()\n");
|
|
|
|
for (i = 0; i < sockets; i++) {
|
|
psock = socket_table[i].psock;
|
|
tcic_setl(TCIC_ADDR, (psock << TCIC_ADDR_SS_SHFT)
|
|
| TCIC_ADDR_INDREG | TCIC_SCF1(psock));
|
|
sstat = tcic_getb(TCIC_SSTAT);
|
|
latch = sstat ^ socket_table[psock].last_sstat;
|
|
socket_table[i].last_sstat = sstat;
|
|
if (tcic_getb(TCIC_ICSR) & TCIC_ICSR_CDCHG) {
|
|
tcic_setb(TCIC_ICSR, TCIC_ICSR_CLEAR);
|
|
quick = 1;
|
|
}
|
|
if (latch == 0)
|
|
continue;
|
|
events = (latch & TCIC_SSTAT_CD) ? SS_DETECT : 0;
|
|
events |= (latch & TCIC_SSTAT_WP) ? SS_WRPROT : 0;
|
|
if (tcic_getw(TCIC_DATA) & TCIC_SCF1_IOSTS) {
|
|
events |= (latch & TCIC_SSTAT_LBAT1) ? SS_STSCHG : 0;
|
|
} else {
|
|
events |= (latch & TCIC_SSTAT_RDY) ? SS_READY : 0;
|
|
events |= (latch & TCIC_SSTAT_LBAT1) ? SS_BATDEAD : 0;
|
|
events |= (latch & TCIC_SSTAT_LBAT2) ? SS_BATWARN : 0;
|
|
}
|
|
if (events) {
|
|
pcmcia_parse_events(&socket_table[i].socket, events);
|
|
}
|
|
}
|
|
|
|
/* Schedule next poll, if needed */
|
|
if (((cs_irq == 0) || quick) && (!tcic_timer_pending)) {
|
|
poll_timer.expires = jiffies + (quick ? poll_quick : poll_interval);
|
|
add_timer(&poll_timer);
|
|
tcic_timer_pending = 1;
|
|
}
|
|
active = 0;
|
|
|
|
pr_debug("interrupt done\n");
|
|
return IRQ_HANDLED;
|
|
} /* tcic_interrupt */
|
|
|
|
static void tcic_timer(u_long data)
|
|
{
|
|
pr_debug("tcic_timer()\n");
|
|
tcic_timer_pending = 0;
|
|
tcic_interrupt(0, NULL);
|
|
} /* tcic_timer */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int tcic_get_status(struct pcmcia_socket *sock, u_int *value)
|
|
{
|
|
u_short psock = container_of(sock, struct tcic_socket, socket)->psock;
|
|
u_char reg;
|
|
|
|
tcic_setl(TCIC_ADDR, (psock << TCIC_ADDR_SS_SHFT)
|
|
| TCIC_ADDR_INDREG | TCIC_SCF1(psock));
|
|
reg = tcic_getb(TCIC_SSTAT);
|
|
*value = (reg & TCIC_SSTAT_CD) ? SS_DETECT : 0;
|
|
*value |= (reg & TCIC_SSTAT_WP) ? SS_WRPROT : 0;
|
|
if (tcic_getw(TCIC_DATA) & TCIC_SCF1_IOSTS) {
|
|
*value |= (reg & TCIC_SSTAT_LBAT1) ? SS_STSCHG : 0;
|
|
} else {
|
|
*value |= (reg & TCIC_SSTAT_RDY) ? SS_READY : 0;
|
|
*value |= (reg & TCIC_SSTAT_LBAT1) ? SS_BATDEAD : 0;
|
|
*value |= (reg & TCIC_SSTAT_LBAT2) ? SS_BATWARN : 0;
|
|
}
|
|
reg = tcic_getb(TCIC_PWR);
|
|
if (reg & (TCIC_PWR_VCC(psock)|TCIC_PWR_VPP(psock)))
|
|
*value |= SS_POWERON;
|
|
dev_dbg(&sock->dev, "GetStatus(%d) = %#2.2x\n", psock, *value);
|
|
return 0;
|
|
} /* tcic_get_status */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int tcic_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
|
|
{
|
|
u_short psock = container_of(sock, struct tcic_socket, socket)->psock;
|
|
u_char reg;
|
|
u_short scf1, scf2;
|
|
|
|
dev_dbg(&sock->dev, "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
|
|
"io_irq %d, csc_mask %#2.2x)\n", psock, state->flags,
|
|
state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
|
|
tcic_setw(TCIC_ADDR+2, (psock << TCIC_SS_SHFT) | TCIC_ADR2_INDREG);
|
|
|
|
reg = tcic_getb(TCIC_PWR);
|
|
reg &= ~(TCIC_PWR_VCC(psock) | TCIC_PWR_VPP(psock));
|
|
|
|
if (state->Vcc == 50) {
|
|
switch (state->Vpp) {
|
|
case 0: reg |= TCIC_PWR_VCC(psock) | TCIC_PWR_VPP(psock); break;
|
|
case 50: reg |= TCIC_PWR_VCC(psock); break;
|
|
case 120: reg |= TCIC_PWR_VPP(psock); break;
|
|
default: return -EINVAL;
|
|
}
|
|
} else if (state->Vcc != 0)
|
|
return -EINVAL;
|
|
|
|
if (reg != tcic_getb(TCIC_PWR))
|
|
tcic_setb(TCIC_PWR, reg);
|
|
|
|
reg = TCIC_ILOCK_HOLD_CCLK | TCIC_ILOCK_CWAIT;
|
|
if (state->flags & SS_OUTPUT_ENA) {
|
|
tcic_setb(TCIC_SCTRL, TCIC_SCTRL_ENA);
|
|
reg |= TCIC_ILOCK_CRESENA;
|
|
} else
|
|
tcic_setb(TCIC_SCTRL, 0);
|
|
if (state->flags & SS_RESET)
|
|
reg |= TCIC_ILOCK_CRESET;
|
|
tcic_aux_setb(TCIC_AUX_ILOCK, reg);
|
|
|
|
tcic_setw(TCIC_ADDR, TCIC_SCF1(psock));
|
|
scf1 = TCIC_SCF1_FINPACK;
|
|
scf1 |= TCIC_IRQ(state->io_irq);
|
|
if (state->flags & SS_IOCARD) {
|
|
scf1 |= TCIC_SCF1_IOSTS;
|
|
if (state->flags & SS_SPKR_ENA)
|
|
scf1 |= TCIC_SCF1_SPKR;
|
|
if (state->flags & SS_DMA_MODE)
|
|
scf1 |= TCIC_SCF1_DREQ2 << TCIC_SCF1_DMA_SHIFT;
|
|
}
|
|
tcic_setw(TCIC_DATA, scf1);
|
|
|
|
/* Some general setup stuff, and configure status interrupt */
|
|
reg = TCIC_WAIT_ASYNC | TCIC_WAIT_SENSE | to_cycles(250);
|
|
tcic_aux_setb(TCIC_AUX_WCTL, reg);
|
|
tcic_aux_setw(TCIC_AUX_SYSCFG, TCIC_SYSCFG_AUTOBUSY|0x0a00|
|
|
TCIC_IRQ(cs_irq));
|
|
|
|
/* Card status change interrupt mask */
|
|
tcic_setw(TCIC_ADDR, TCIC_SCF2(psock));
|
|
scf2 = TCIC_SCF2_MALL;
|
|
if (state->csc_mask & SS_DETECT) scf2 &= ~TCIC_SCF2_MCD;
|
|
if (state->flags & SS_IOCARD) {
|
|
if (state->csc_mask & SS_STSCHG) reg &= ~TCIC_SCF2_MLBAT1;
|
|
} else {
|
|
if (state->csc_mask & SS_BATDEAD) reg &= ~TCIC_SCF2_MLBAT1;
|
|
if (state->csc_mask & SS_BATWARN) reg &= ~TCIC_SCF2_MLBAT2;
|
|
if (state->csc_mask & SS_READY) reg &= ~TCIC_SCF2_MRDY;
|
|
}
|
|
tcic_setw(TCIC_DATA, scf2);
|
|
/* For the ISA bus, the irq should be active-high totem-pole */
|
|
tcic_setb(TCIC_IENA, TCIC_IENA_CDCHG | TCIC_IENA_CFG_HIGH);
|
|
|
|
return 0;
|
|
} /* tcic_set_socket */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int tcic_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
|
|
{
|
|
u_short psock = container_of(sock, struct tcic_socket, socket)->psock;
|
|
u_int addr;
|
|
u_short base, len, ioctl;
|
|
|
|
dev_dbg(&sock->dev, "SetIOMap(%d, %d, %#2.2x, %d ns, "
|
|
"%#llx-%#llx)\n", psock, io->map, io->flags, io->speed,
|
|
(unsigned long long)io->start, (unsigned long long)io->stop);
|
|
if ((io->map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
|
|
(io->stop < io->start)) return -EINVAL;
|
|
tcic_setw(TCIC_ADDR+2, TCIC_ADR2_INDREG | (psock << TCIC_SS_SHFT));
|
|
addr = TCIC_IWIN(psock, io->map);
|
|
|
|
base = io->start; len = io->stop - io->start;
|
|
/* Check to see that len+1 is power of two, etc */
|
|
if ((len & (len+1)) || (base & len)) return -EINVAL;
|
|
base |= (len+1)>>1;
|
|
tcic_setw(TCIC_ADDR, addr + TCIC_IBASE_X);
|
|
tcic_setw(TCIC_DATA, base);
|
|
|
|
ioctl = (psock << TCIC_ICTL_SS_SHFT);
|
|
ioctl |= (len == 0) ? TCIC_ICTL_TINY : 0;
|
|
ioctl |= (io->flags & MAP_ACTIVE) ? TCIC_ICTL_ENA : 0;
|
|
ioctl |= to_cycles(io->speed) & TCIC_ICTL_WSCNT_MASK;
|
|
if (!(io->flags & MAP_AUTOSZ)) {
|
|
ioctl |= TCIC_ICTL_QUIET;
|
|
ioctl |= (io->flags & MAP_16BIT) ? TCIC_ICTL_BW_16 : TCIC_ICTL_BW_8;
|
|
}
|
|
tcic_setw(TCIC_ADDR, addr + TCIC_ICTL_X);
|
|
tcic_setw(TCIC_DATA, ioctl);
|
|
|
|
return 0;
|
|
} /* tcic_set_io_map */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int tcic_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
|
|
{
|
|
u_short psock = container_of(sock, struct tcic_socket, socket)->psock;
|
|
u_short addr, ctl;
|
|
u_long base, len, mmap;
|
|
|
|
dev_dbg(&sock->dev, "SetMemMap(%d, %d, %#2.2x, %d ns, "
|
|
"%#llx-%#llx, %#x)\n", psock, mem->map, mem->flags,
|
|
mem->speed, (unsigned long long)mem->res->start,
|
|
(unsigned long long)mem->res->end, mem->card_start);
|
|
if ((mem->map > 3) || (mem->card_start > 0x3ffffff) ||
|
|
(mem->res->start > 0xffffff) || (mem->res->end > 0xffffff) ||
|
|
(mem->res->start > mem->res->end) || (mem->speed > 1000))
|
|
return -EINVAL;
|
|
tcic_setw(TCIC_ADDR+2, TCIC_ADR2_INDREG | (psock << TCIC_SS_SHFT));
|
|
addr = TCIC_MWIN(psock, mem->map);
|
|
|
|
base = mem->res->start; len = mem->res->end - mem->res->start;
|
|
if ((len & (len+1)) || (base & len)) return -EINVAL;
|
|
if (len == 0x0fff)
|
|
base = (base >> TCIC_MBASE_HA_SHFT) | TCIC_MBASE_4K_BIT;
|
|
else
|
|
base = (base | (len+1)>>1) >> TCIC_MBASE_HA_SHFT;
|
|
tcic_setw(TCIC_ADDR, addr + TCIC_MBASE_X);
|
|
tcic_setw(TCIC_DATA, base);
|
|
|
|
mmap = mem->card_start - mem->res->start;
|
|
mmap = (mmap >> TCIC_MMAP_CA_SHFT) & TCIC_MMAP_CA_MASK;
|
|
if (mem->flags & MAP_ATTRIB) mmap |= TCIC_MMAP_REG;
|
|
tcic_setw(TCIC_ADDR, addr + TCIC_MMAP_X);
|
|
tcic_setw(TCIC_DATA, mmap);
|
|
|
|
ctl = TCIC_MCTL_QUIET | (psock << TCIC_MCTL_SS_SHFT);
|
|
ctl |= to_cycles(mem->speed) & TCIC_MCTL_WSCNT_MASK;
|
|
ctl |= (mem->flags & MAP_16BIT) ? 0 : TCIC_MCTL_B8;
|
|
ctl |= (mem->flags & MAP_WRPROT) ? TCIC_MCTL_WP : 0;
|
|
ctl |= (mem->flags & MAP_ACTIVE) ? TCIC_MCTL_ENA : 0;
|
|
tcic_setw(TCIC_ADDR, addr + TCIC_MCTL_X);
|
|
tcic_setw(TCIC_DATA, ctl);
|
|
|
|
return 0;
|
|
} /* tcic_set_mem_map */
|
|
|
|
/*====================================================================*/
|
|
|
|
static int tcic_init(struct pcmcia_socket *s)
|
|
{
|
|
int i;
|
|
struct resource res = { .start = 0, .end = 0x1000 };
|
|
pccard_io_map io = { 0, 0, 0, 0, 1 };
|
|
pccard_mem_map mem = { .res = &res, };
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
io.map = i;
|
|
tcic_set_io_map(s, &io);
|
|
}
|
|
for (i = 0; i < 5; i++) {
|
|
mem.map = i;
|
|
tcic_set_mem_map(s, &mem);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct pccard_operations tcic_operations = {
|
|
.init = tcic_init,
|
|
.get_status = tcic_get_status,
|
|
.set_socket = tcic_set_socket,
|
|
.set_io_map = tcic_set_io_map,
|
|
.set_mem_map = tcic_set_mem_map,
|
|
};
|
|
|
|
/*====================================================================*/
|
|
|
|
module_init(init_tcic);
|
|
module_exit(exit_tcic);
|