![]() Initialise the parent of UARTs to PLLP and disabling clock by default. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> |
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clk-audio-sync.c | ||
clk-divider.c | ||
clk-periph-gate.c | ||
clk-periph.c | ||
clk-pll-out.c | ||
clk-pll.c | ||
clk-super.c | ||
clk-tegra20.c | ||
clk-tegra30.c | ||
clk.c | ||
clk.h | ||
Makefile |